Xycom XVME-400 Manual page 30

XVME-400/40l/490/491 Manual
October, 1989
Module Base Address
Register
1OOOH
I
The XVME-400/401/490/491 is an odd byte only slave,
and as such, the module will not respond to even address,
single-byte accesses. However, word accesses may be
used, with the understanding that only the odd byte of
the word is used to exchange data. If word accesses are
used, the register offsets listed in Table 3-1 would all be
decremented by 1.
Table 3-1 lists the offsets for the internal registers of all four serial channels on the
XVME-400 (two channels per SCC serial chip).
Off set Address
Hex Decimal
1 1
3
3
5 5
7 7
9 9
B 1 1
D
1 3
F 1 5
The registers in the 8530 are accessed in a two-step process. The first step is to write a
pointer to one of the four control registers listed in Table 3-l. After the pointer is written
to a control register, the next read or write
desired 8530 register.
and their pointers.
Single-step access of a data register is performed by reading or writing to any of the four
data registers. The XVME-400/401/490/491
access the 8530 registers RRS or WRS directly, independent of the state of the pointer bits.
Register Offset
07H
+
Table 3-1. Register Offsets
.
Serial Channel 3 Control Register
Serial Channel 3 Data Register
Serial Channel 2 Control Register
Serial Channel 2 Data Register
Serial Channel 1 Control Register
Serial Channel 1 Data Register
Serial Channel 0 Control Register
Serial Channel 0 Data Register
Refer to the 8530 Manual for a description of the 8530 registers
=
NOTE
Module Register
to
the same control register will access the
will automatically set D/C high and will
3-2
Serial Channel 2 Data
1007H
(SCC #2 Channel B)
(SCC #2 Channel B)
(SCC #2 Channel A)
(SCC #2 Channel A)
(SCC #l Channel B)
(SCC #l Channel B)
(SCC #l Channel A)
(SCC #l Channel
A)