Fujitsu M2361A Customer Engineering Manual page 170

(6) VFO
The Variable Frequency Oscillator (VFO) output is synchronized with VCOI
signal from the servo information during non-read operation, and with the
Raw Data (RAWD) signal from the data track during a read operation. The
block diagram of the VFO circuits is shown in Figure 4.6.35.
The VFO are composed of the following circuit.
• VFO Input Multiplexer
• Time-Margin Measurement (TMG) One-Short
• Reference One-Shot
• Phase compare Latch
• Phase Comparator and Charge Pump
• Low Pass Filter and Buffer
• Voltage Controlled Oscillator (VCO)
a. VFO Input Multiplexer
The VFO input multiplexer controls the VFO input. During an initial
seek operation or a RTZ operation, this circuit inhibits an input of
data into the VFO circuit by enabling the Filter Squelch (FLTSQ)
signal. This causes the VCO to oscillate at a free-running
frequency. After an initial seek operation or a RTZ operation, the
VFO Input multiplexer controls the transmission of the VCOl or RAWD
signals into the VFO circuit.
During a non-read operation, the signal is applied to the VFO
circuits by the enabling of the Servo Mode (SVMD) signal. During a
read operation, the RAWDT signal is applied to the VFO circuits by
disabling the SVMD signal. The VFO input multiplexer output, Data
Input 1 (DTIN1), is applied to the TMG One-shot circuit.
b. TMG One-shot
The TMG One-shot circuit issues a Data Input 2 (DTIN2) signal to the
Phase Comparator, and Reference One Shot circuit. It also issues
Delayed Data (DLDT) signal to the Data Window circuit. The timing
relation between DTIN2 and DLDT signals adjusted by potentiometer RV4
determines the read margin. (Refer to Figure 4.6.37)
c. Reference One-shot
The leading edge of the DTIN2 signal triggers the Reference One-shot,
which issues a 16 ns Reference Pulse (REFP) signal to the Phase
Comparator Charge Pump circuit.
d. Phase-Compare Latch
The leading edge of the DTIN2 signal sets the Phase-Compare Latch and
the negative-going edge of *2F clock (*2F CLK) resets it. The
Phase-Compare Latch issues a Phase-Compare Latch Output (PCLO) signal
to the Phase Comparator Charge Pump circuit.
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