Introduction; References; Hardware Overview - Texas Instruments OMAP35 Series User Manual

10.1. Introduction

TI OMAP35x has a host cum gadget controller MUSB OTG,an EHCI and its
companion OHCI controller.There are three USB ports which are to be controlled
by either EHCI or OHCI controller individually. In ES2.0/2.1 silicon all the three
port can either be configured in PHY mode or in TLL mode at a time.This
limitation got resolved in ES3.0/3.1 silicon where PHY/TLL mode selection can
be done on per port basis.
The salient features of the MUSB OTG controller are:
•
•
•
•
•
•
•
•
•
•

10.1.1. References

1.

10.1.2. Hardware Overview

The OMAP35x MUSB OTG controller sits on the L3 and L4 interconnect. It can
be an L3 master while performing DMA transfers and an L4 target when host
CPU/DMA engine is the master.
The OMAP35x EVM has an OTG compliant USB PHY from NXP (ISP 1504). The
USB controller in the SoC is connected to the NXP PHY located on the EVM. A
mini-AB USB port connects to the PHY. Hence, there is only one root port for
the USB controller.
Version 02.01.01.08
High/full speed operation as USB peripheral.
High/full/low speed operation as Host controller.
The host controller for a multi-point USB system (when connected via hub).
USB On-The-Go compliant USB controller.
15 Transmit and 15 Receive Endpoints other than the mandatory Control
Endpoint 0.
16 Kilobytes of Endpoint FIFO RAM for USB packet buffering.
Double buffering FIFO.
Support for Bulk split and Bulk combine
Support for high bandwidth Isochronous transfer
Dual Mode HS DMA controller with 8 channels.
OMAP35x Technical Reference Manual
Platform Support Products
USB Driver
Introduction
183