Application Notes - Advantech SOM-ETX Series Design Manual

Table 5.7 PCI Clock Signals Routing Summary
Trace PCI Routing Requirements
Impedance
55 Ohm 6 mils width, 50 mils spacing (based on
10% stackup ssumptions)
Note:
Clocks skew between PCI slots/devices should be less than 2ns@33MHz and
1ns@66MHz. The recommend value of the clock trace tolerance of W3(a,b,c,d) is 5
inch(Max).

5.1.4 Application Notes

5.1.4.1 REQ/GNT
These signals are used only by bus-mastering PCI devices. Most SOM-ETX modules
do not have enough REQ/GNT pairs available to support a bus-mastering device at
every slot position. A PCI arbiter design is recommended when extra REQ/GNT pairs
are required. Figure 5.5 show the example design for PCI arbiter :
FRAME#
STOP#
PCIREQ#1
PCIGNT#1
MS1PREQ#1
MS1PGNT#1
MS1PREQ#2
MS1PGNT#2
MS1PREQ#3
MS1PGNT#3
If there are less than four REQ/GNT pairs available for external devices, they will be
assigned starting with the REQ0#/GNT0# pair. Therefore, external bus-mastering
devices should be placed in the lowest numbered slot positions and non-bus
mastering devices should be placed in the highest-numbered slot positions. Refer to
Chapter 2.X.X REQ/GNT for the details
Advantech SOM-ETX Design Guide
1
FRAME#
2
STOP#
3
SY SREQ#
4
SY SGNT#
5
PCIREQ1# PCICLKI
7
PCIGNT1# RESET#
8
PCIREQ2# PCICLK0
10
PCIGNT2# PCICLK1
11
PCIREQ3# PCICLK2
12
PCIGNT3# PCICLK3
PCICLK4
13
VC3A
16
VC3B
14
VC5A
15
VC5B
MS-1
Figure 5-5 Design Example PCI Arbiter
Chapter 5 Carrier Board Design Guidelines
Topology Maximum trace
Length
W1:0.5 inch
2~4 W2:5 inch
Devices W3(a,b,c,d):15 inch
W4:0.5 inch
W5:as long as need
28
AVCC
21
VCC
9
VCC
MS1PCICLK
27
PCIRST#
26
23 33
22 33
20 33
19 33
18 33
25
AVSS
24
VSS
17
VSS
6
VSS
Damping
Resistor
R1: 33
ohm
R2: 33
ohm
PCICLK1
PCICLK2
PCICLK3
67