Ide0/Ide1; Signal Description - Advantech SOM-ETX Series Design Manual

SOM-ETX
LCDON
VGA
BACKON

5.7 IDE0/IDE1

SOM-ETX provides two IDE interface, IDE0/IDE1.

5.7.1 Signal Description

Table 5.15 shows SOM-ETX PCI IDE signals, including pin number, signals, I/0 and
descriptions.
Table 5.15 IDE signals description
Pin Signal
PIDE_D[0..15]
-
SIDE_D[0..15]
D38,40,3
6 PIDE_A[0..2]
D31,37,2 SIDE_A[0..2]
9
D32 PIDE_CS#1
D27 SIDE_CS#1
D30 PIDE_CS#3
D25 SIDE_CS#3
D56 PIDE_DRQ
D53 SIDE_DRQ
D46 PIDE_ACK#
D43 SIDE_ACK#
D46 PIDE_RDY
D45 SIDE_RDY
D52 PIDE_IOR#
D47 SIDE_IOR#
84
Advantech SOM-ETX Design Guide
Damping
TTL
10~ 33 Ohm
Figure 5-21 TTL LCD Layout Guideline
I/O Description
Primary/ Secondary IDE ATA Data Bus. These are the Data
I/O
pins connected to Primary Channel.
IDE ATA Address Bus. These are the Address pins
O
connected to Secondary Channel.
IDE Chip Select 1 for Channel 0. This is the Chip Select 1
O command output pin to enable the IDE device to watch the
Read/Write Command.
IDE CHIP SELECT 3 FOR CHANNEL 1. THIS IS THE CHIP
O SELECT 3 COMMAND OUTPUT PIN TO ENABLE THE IDE
DEVICE TO WATCH THE READ/WRITE COMMAND
IDE DMA Request for IDE Master. This is the input pin from
the IDE DMA request to do the IDE Master Transfer. It will
I
active high in DMA or Ultra-33 mode and always be inactive
low in PIO mode.
IDE_ACK# for IDE Master. This is the output pin to grant the
O IDE DMA request to begin the IDE Master Transfer in DMA
or Ultra-33 mode.
IDE Ready. This is the input pin from the IDE Channel to
indicate the IDE device is ready to terminate the IDE
command in PIO mode. The IDE device can de-assert this
input (logic 0) to expand the IDE command if the device is
I not ready. In Ultra-33 mode, this pin has different functions.
In read cycle, IDE device will drive this signal as Data Strobe
(DSTROBE) to use by IDE Bus master to strobe the input
data. In write cycles, this pin is used by IDE device to notify
IDE Bus master as DMA Ready.
IDE_IOR# Command. This is the IOR# command output pin
to notify the IDE device to assert the Read Data in PIO and
O
DMA mode. In Ultra-33 mode, this pin has different function.
In read cycle, this pin is used by IDE-Bus-master to notify
Chapter 5 Carrier Board Design Guidelines
+5V +3.3V
Bead
Power
VDD
Transfer
30Ohm
@100Mhz
Buffer IC
for Level
Shift
120 Ohm
@100MHz
10pF
Digital GND Chassis GND
Carryboard
TTL LCD
Connector
Inverter
Connector