Design Guideline - Advantech SOM-ETX Series Design Manual

B20,64,9
DREQ[0,1
1,70,16,1
,2,3,5,6,7]
2,8
B22,66,4
DACK[0,1,
6,72,18,1
2,3,5,6,7]#
4,10
B44 TC
IRQ[3..7,9
-
,15]

5.4.2 Design Guideline

5.4.2.1 Interrupt and DMA signals
Eight-bit ISA devices will not need the signals on the lower part of the connector (the
C and D pin numbers),but the additional interrupts and DMA channels available on
this part of the connector will make system configuration more flexible.
Many ISA devices already contain a plug-and-play matrix that allows routing internal
interrupt or DMA requests to most of the possible destinations on the ISA bus. For
simpler devices, which do not implement internal interrupt and DMA routing, it is
often worthwhile to provide jumper blocks or resistor options.
These mechanical switching arrangements allow changing the devices interrupt and
DMA assignments in case a resource conflict arises later in the development of the
system.
ISA devices generally are not able to share interrupts. Because of this, ISA device
drivers are rarely written with interrupt sharing in mind. Systems with many ISA
devices tend to run out of interrupt lines. Solving this problem can require specialized
software and hardware.
Advantech SOM-ETX Design Guide
The asynchronous DMA request inputs are used by external
devices to indicate when they need service from the CPU modules
DAM controllers. DREQ0..3 are used for transfers between 8-bit I/O
I adapters and system memory. DREQ5..7 are used for transfers
between 16-bit I/O adapters and system memory. DRQ4 is not
available externally. All DRQ pins have pull-up resistors on the
CPU modules.
DMA acknowledge 0..3 and 5.7 are used to acknowledge DMA
O
requests. They are active-low.
The active-high output TC indicates that one of the DMA channels
O
has transferred all data.
These are the asynchronous interrupt request lines. IRQ0, 1, 2 and
8 are not available as external interrupts because they are used
internally on the CPU module. All IRQ signals are active-high. The
interrupt requests are prioritized. IRQ9 through IRQ12 and IRQ14
I through IRQ15 have the highest priority (IRQ9 is the highest). IRQ3
through IRQ7 have the lowest priority (IRQ7 is the lowest). An
interrupt request is generated when an IRQ line is raised from low
to high. The line must be held high until the CPU acknowledges the
interrupt request (interrupt service routine).
Chapter 5 Carrier Board Design Guidelines 77