Chapter 5 Carrier Board Design Guidelines; Pci-Bus; Signal Description - Advantech SOM-ETX Series Design Manual

Chapter 5 Carrier Board Design Guidelines

5.1 PCI-Bus

SOM-ETX provides a PCI Bus interface that is compliant with the PCI Local Bus
Specification, Revision 2.2. The implementation is optimized for high-performance
data streaming when SOM-ETX is acting as either the target or the initiator on the
PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus
Specification, Revision 2.2.

5.1.1 Signal Description

Table 5.1 shows SOM-ETX PCI bus signal, including pin number, signals, I/0, and
descriptions.
Table 5.1 PCI Signal Description
Pin Signal
A7,8,3,4 PCICLK[1..4]
A22,15,1
PCIREQ[0..3]
3,9
A17,14,1
GNT[0..3]
1,10
- AD[0..31]
A31,49,7
CBE[0..3]
0,82
A53 PAR
A54 SERR#
A55 PERR#
A57 PME#
LOCK#
A59
DEVSEL#
A60
TRDY#
A61
IRDY#
A63
STOP#
A64
FRAME#
A65
PCIRST#
A93
A97,98,9
INT[A.D]
5,96
Advantech SOM-ETX Design Guide
I/O Description
PCI clock outputs for up to 4 external PCI slots or devices.
I
Bus Request signals for up to 4 external bus mastering PCI
I devices. When asserted, it means a PCI device is requesting
PCI bus ownership from the arbiter.
Grant signals to PCI Masters. When asserted by the arbiter,
O
the PCI master has been granted ownership of the PCI bus.
PCI Address and Data Bus Lines. These lines carry the
I/O
address and data information for PCI transactions.
PCI Bus Command and Byte Enables. Bus command and
byte enables are multiplexed in these lines for address and
I/O
data phases, respectively.
Parity bit for the PCI bus.
I/O
System Error. Asserted for hardware error conditions such
OD
as parity errors detected in DRAM.
Parity Error. For PCI operation per exception granted by PCI
I/O
2.1 Specification.
OD Power management event.
Lock Resource Signal. This pin indicates that either the PCI
I/O
master or the bridge intends to run exclusive transfers.
Device Select. When the target device has decoded the
I/O
address as its own cycle, it will assert DEVSEL#.
Target Ready. This pin indicates that the target is ready to
I/O
complete the current data phase of a transaction.
Initiator Ready. This signal indicates that the initiator is ready
I/O
to complete the current data phase of a transaction.
Stop. This signal indicates that the target is requesting that
I/O
the master stop the current transaction.
Cycle Frame of PCI Buses. This indicates the beginning and
I/O
duration of a PCI access.
PCI Bus Reset. This is an output signal to reset the entire
I
PCI Bus. This signal is asserted during system reset.
PCI interrupts from CPU-PCI bridge.
OD
Chapter 5 Carrier Board Design Guidelines 61