Layout Requirement - Advantech SOM-ETX Series Design Manual

5.10.3

Layout Requirement

5.10.3.1 EMI Consideration
I/Os like LPT ports/Floppy and COM ports should be physically isolation from digital
circuitry, analog circuitry, and power and ground planes. This isolation prevents noise
sources located elsewhere on the PCB from corrupting susceptible circuit. An
example is power plane noise from digital circuits entering the power pins of analog
devices, audio components, I/O filters and interconnects, and so on.
Each and every I/O port (or section) must have a partitioned ground/power plane.
Lower frequency I/O ports may be bypassed with high-frequency capacitors located
near the connectors.
Trace routing on the PCB must be controlled to avoid recouping RF currents into the
cable shield. A clean ground must be located at the point where cables leave the
system. Both power and ground planes must be treated equally, as these planes act
as a path for RF return currents.
To implement a clean ground, use of a partition or moat is required. The clean area
may be:
1. 100% isolated with I/O signals entering and exiting via an isolation
transformer or an optical device.
2. Data line filtered; or
3. Filtered through a high-impedance common-mode inductor (choke) or
protected by a ferrite bead-on-lead component.
5.10.3.2 ESD Protection
PCB must incorporate protection against electrostatic discharge (ESD) events that
might enter at I/O signal and electrical connection points. The goal is to prevent
component or system failures due to externally sourced ESD impulses that may be
propagated through both radiated and conducted mechanisms.
Several commonly used design techniques for ESD protection that may be
implemented on a PC for high-level pulse suppression include the following:
1. High voltage capacitors. These disc-ceramic capacitors must be rated at
1500V (1 KV) minimum. Lower-voltage capacitors may be damaged by the
first occurrence of an ESD pulse. This capacitor must e located immediately
adjacent to the I/O connector.
2. TVS components. These are semiconductor devices specifically designed
for transient voltage suppression applications. They have the advantage of
a stable and fast time constant to avalanche, and a stable clamping level
after avalanche.
3. LC filters. An LC filter is a combination of an inductor and a capacitor to
ground. This constitutes a low-pass LC filter that prevents high-frequency
ESD energy from entering the system. The inductor presents a high-
impedance source to the pulse, thus attenuating the impulse energy that
enters the system. The capacitor, located on the input side of the inductor
will shunt high-frequency ESD spectral level components to ground. An
additional benefit of this circuit combination is enhancement of radiated EMI
noise suppression.
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Advantech SOM-ETX Design Guide
Chapter 5 Carrier Board Design Guidelines