Isa-Bus; Signal Description - Advantech SOM-ETX Series Design Manual

5.3.3.3 EMI Consideration
Any signals entering or leaving the analog area must cross the ground split through
bead in the area where the analog ground is attached to the main motherboard
ground. That is, no signal should cross the split/gap between the ground planes,
which would cause a ground loop, thereby greatly increasing EMI emissions and
degrading the analog and digital signal quality.
5.3.3.4 Analog Power and Signals Routing
Note that analog power and signal traces should be routed over the analog
ground plane.

5.4 ISA-Bus

SOM-ETX provides ISA bus for traditional applications.

5.4.1 Signal Description

Table 5.11 shows SOM-ETX ISA bus signal, including pin number, signals, I/0, and
descriptions.
Table 5.11 ISA Bus signals description
Pin Signal
- SD[0..15]
- SA[0..19]
B37 SBHE#
B42 BALE
B82 AEN
B19 MEMR#
B80 SMEMR#
B17 MEMW#
B86 SMEMW#
B74 IOR#
Advantech SOM-ETX Design Guide
I/O Description
These signals provide data bus bits 0 to 15 for any peripheral
devices. All 8-bit devices use SD0[0..7] for data transfers. 16-bit
devices use SD[0..15]. To support 8-bit devices, the data on
I/O
SD[8..15] is gated to SD[0..7] during 8-bit transfers to these
devices. 16-bit CPU cycles will be automatically converted into two
8-bit cycles for 8-bit peripherals.
Address bits 0 through 15 are used to address I/O devices.
Address bits 0 through 19 are used to address memory within the
I/O system. These 20 address lines, in addition to LA[17..23] allow
access of up to 16MB of memory. SA[0..19] are gated on the ISA-
bus when BALE is high and latched on to the falling edge of BALE.
Bus High Enable indicates a data transfer on the upper byte of the
I/O data bus SD[8..15]. 16-bit I/O devices use SBHE# to enable data
bus buffers on
BALE is an active-high pulse generated at the beginning of any bus
O cycle initiated by a CPU module. It indicates when the SA[0..19],
LA17.23, AEN, and SBHE# signals are valid.
AEN is an active-high output that indicates a DMA transfer cycle.
O
Only resources with a active
MEMR# instructs memory devices to drive data onto the data bus.
I/O
MEMR# is active for all memory read cycles.
SMEMR# instructs memory devices to drive data onto the data bus.
O SMEMR# is active for memory read cycles to addresses below
1MB.
MEMW# instructs memory devices to store the data present on the
I/O
data bus. MEMW# is active for all memory write cycles.
SMEMW# instructs memory devices to store the data present on
O the data bus. SMEMW# is active for all memory write cycles to
address below 1MB.
I/O read instructs an I/O device to drive its data onto the data bus. It
I/O
may be driven by the CPU or by the DMA controller. IOR# is
Chapter 5 Carrier Board Design Guidelines 75