Intel M20MYP1UR Integration And Service Manual page 78

Intel® Server System M20MYP1UR System Integration and Service Guide
Post Code
(Hex) Nibble
Upper
AE
Lower
Upper
AF
Lower
PEI Phase
Upper
10
Lower
Upper
11
Lower
Upper
15
Lower
Upper
19
Lower
MRC Progress Codes
Upper
31
Lower
Upper
32
Lower
Upper
33
Lower
Upper
4F
Lower
DXE Phase
Upper
60
Lower
Upper
62
Lower
Upper
68
Lower
Upper
69
Lower
78
LED 3
(MSB) LED 2 LED 1
1 0 1
1 1 1
1 0 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
1 0 0
0 0 1
0 0 0
0 0 1
0 0 1
0 0 1
0 0 1
0 1 0
1 1 1
0 1 1
0 0 0
0 1 1
0 0 1
0 1 1
1 0 0
0 1 1
1 0 0
LED 0
(LSB)
0
Coherency settings
0
0
Intel UPI initialization done
1
1
PEI core
0
1
CPU PEIM
1
1
Platform type initialization
1
1
Platform PEIM Initialization
1
1
Memory installed
1
1
CPU PEIM (CPU initialization)
0
1
CPU PEIM (cache initialization)
1
0
DXE IPL started
1
0
DXE core started
0
0
DXE setup initialization
0
0
DXE PCI host bridge initialization
0
0
DXE NB initialization
1
Description