Toshiba TECRA 9100 Series Maintenance Manual page 23

1.2 System Unit Block Diagram
The system unit is composed of the following major components:
Processor
• Intel Mobile Pentium 4 Processor 1.70GHz
– Processor core speed: 1.70GHz (Performance Mode at 1.30V) and
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 12KB instruction cache and 8KB write-
– Integrated L2 cache memory: 512KB ECC protected cache data array,
– Integrated NDP
• Intel Mobile Pentium 4 Processor 1.60GHz
– Processor core speed: 1.60GHz (Performance Mode at 1.30V) and
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 12KB instruction cache and 8KB write-
– Integrated L2 cache memory: 512KB ECC protected cache data array,
– Integrated NDP
Memory
Two BTO/CTO-compatible expansion memory slots are provided. Expansion up to
1024 MB is available.
• DDR-SDRAM (Double Data Rate - Synchronous DRAM @133MHz)
• 128 MB/256/512 MB selectable
− 128 MB
− 256 MB (256Mbit 16M×16bit, 8P)
− 512 MB (512Mbit 32M×16bit, 8P) or (256Mbit 16M×16bit, 16P)
• 200 pin, SO Dual In-line Memory Modules. (SO-DIMM)
• 2.5 volt operation
• No parity bit
• Data transfer is 64-bit width
TECRA 9100 Maintenance Manual (960-347)
1.20GHz (Battery Optimized Mode at 1.20V)
back data cache, 4-way set associative
8-way set associative
1.20GHz (Battery Optimized Mode at 1.20V)
back data cache, 4-way set associative
8-way set associative
(128Mbit 8M×16bit, 8P) or (16M×16bit, 4P)
1 Hardware Overview
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