Table B-1 Memory Allocations; Table B-2 Dsimm Dram Densities - Sun Microsystems SPARCstation 20 Service Manual

The following sections provide brief descriptions of DSIMMs, VSIMMs, and
NVSIMMs, and identifies the maximum available memory capacities based on
possible memory allocations.
Memory Allocations
TABLE B-1
Memory DSIMM
Allocation
8 (max.)
7
7
6
6
DSIMM
The SPARCstation 20 memory system has a 144-bit-wide data path. The
144-bit-wide path is divided into a 128-bit-wide data path and 16 bits of error
correcting code (ECC). Through the Scalable Memory Controller (SMC), the
60-nanosecond DSIMMs receive control, address information, and data. The
maximum available DSIMM memory capacities, based upon possible memory
allocations, are as follows:
Eight DSIMMs, zero VSIMMs, zero DVSIMMS: 8 x 64 Mbytes or 512 Mbytes
Seven DSIMMS with one VSIMM or one DVSIMM: 7 x 64 Mbytes or 448 Mbytes
Six DSIMMS with two VSIMMs or one VSIMM and one DVSIMM: 6 x 64 Mbytes
or 384 Mbytes
lists the DSIMM DRAM densities supported by the SMC.
TABLE B-2
illustrates the DSIMM memory system.
DSIMM DRAM Densities
TABLE B-2
RAM Density
4-Mbit 1M x 4
8-Mbit 2M x 4
16-Mbit 4M x 4
VSIMM NVSIMM
0 0
1 0
0 1 (max.)
2 (max.) 0
1 1
Number of RAMs Capacity
36 16 Mbytes
36 32 Mbytes
36 64 Mbytes
Appendix B
FIGURE B-2
Type
ECC DRAM
ECC DRAM
ECC DRAM
Functional Description 199