A Quad B Pulse Interface; Overview; Technical Data; Connection - YASKAWA S-V Seres User Manual

5 Encoder Interfaces

5.1.1 Overview

5.1

A quad B Pulse interface

5.1.1 Overview
A quad B pulse signals is counted by each edges in the master. The interface block diagram is shown below.
A quad B
Pulse
encoder
5.1.2

Technical Data

Items
Encoder Supply
Incremental Encoder
Input
5.1.3

Connection

No
1
2
3
4
5
6
7
8
9
10
11
12
13
*1 Without hall sensor, do not connect to any signals. With hall sensor, please refer to section 6-1, too.
*2 Pins denoted as N.C. do not connect to any signals.
5-2
REF
A
B
.
Output voltage
Signal form
Evaluation
Max. input frequency
Max. counter frequency
Max. reference frequency 1 MHz
Distance between edges
Differential voltage
Signal Pin Function
N.C. *2
N.C. *2
V Hall Signal V + *1
U Hall Signal U + *1
/C(Z) Pulse /C(Z)
C(Z) Pulse C(Z)
- N.C. *2
PG+5V Power
PG+5V Power
PG+5V Power
PG_0V Ground
PG_0V Ground
PG_0V Ground
Encoder Master
FPGA
Description
Typically 5 V
Square wave pulse
4x
1 MHz
4 MHz
0.2 µsec or more
0.2 V or more
Dir. No Signal
OUT 14 -
OUT 15 -
IN 16 W
IN 17 PG_0V
- 18 -
- 19 -
- 20 -
OUT 21 -
OUT 22 -
OUT 23 A
- 24 /A
- 25 B
- 26 /B
Servo
Serial
I/F
Pin Function Dir.
N.C. *2 I/O
N.C. *2 I/O
Hall Signal W + *1 IN
Ground -
N.C. *2 -
N.C. *2 -
N.C. *2 -
N.C. *2 -
N.C. *2 -
Pulse A -
Pulse /A -
Pulse B -
Pulse /B -