Supermicro X10DBT User Manual page 83

Chapter 4: AMI BIOS
DDR Voltage Level
Select Auto for the BIOS to set the voltage settings for all DDR3 memory mod-
ules. Select Force to 1.50V to force all DDR3 memory modules to operate at
1.50V. The options are Auto and Force to 1.50V.
Advanced Clk (Clock) Training
Select Enable to support Advanced Clock Training, which will allow the memory
command line to be synchronized with the clock line to enhance memory per-
formance. The options are Enable and Disable.
Perbit (Per-bit) Deskew Training
Select Enable to support Perbit Deskew Training, which will allow the memory
controller to include various adjustable delay circuits in both Read and Write
paths on a per-bit base for effective memory interface to maximize memory
performance. The options are Disable and Enable.
0DT (On-Die Termination) Timing Mode
Use this feature to configure the timing mode setting for the ODT (On-Die Ter-
mination) where the termination resistor for impedance matching in transmission
lines is located inside a chip instead of on a printed circuit board. The options
are Aggressive Timing and Conservative Timing.
MxB Rank Sharing Mapping
Use this feature to select the address-mapping setting for memory-rank sharing
to enhance extended multimedia platform performance. The options are Maxi-
mum Performance and Maximum Margin.
DIMM Vref. (Voltage Reference) Circuit
This feature allows the user to decide how to configure the voltage reference
point (gate) for a DDR3 memory module. The options are Internal and External.
BIOS VMSE Reset
If this feature is set to Enable, BIOS settings pertaining to the Intel Scalable
Memory Interconnect 2 (Intel SMI 2) controller will be reset to improve system
performance. The options are Disable and Enable.
Save JCK Error Longs
Select Enable to save the JCK Error log at each system reset caused by system
firmware. The options are Enable and Disable.
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