Supermicro X10DBT User Manual page 68

X10DBT/X10DBT-T User's Manual
Adjacent Cache Prefetch (Available when supported by the CPU)
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.
Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options
are Disable and Enable.
Note: Please reboot the system for changes on this setting to take effect.
Please refer to Intel's web site for detailed information.
DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)
If this item is set to Enable, the DCU Streamer Prefetcher will prefetch data streams
from the cache memory to the DCU (Data Cache Unit) to speed up data access-
ing and processing for CPU performance enhancement. The options are Disable
and Enable.
DCU IP Prefetcher
If this feature is set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will
prefetch IP addresses to improve network connectivity and system performance.
The options are Enable and Disable.
DCU Mode
Use this feature to set the data-prefecting mode for the DCU (Data Cache Unit).
The options are 32KB 8Way Without ECC and 16KB 4Way With ECC.
Direct Cache Access (DCA)
Select Enable to use Intel DCA (Direct Cache Access) Technology to improve the
efficiency of data transferring and accessing. The options are Enable and Disable.
DCA Prefetch Delay
A DCA Prefetcher is used with a TOE (TCP/IP Offload Engine) adapter to prefetch
data in order to shorten execution cycles and maximize data processing efficiency.
Prefetching data too frequently can saturate the cache directory and delay neces-
sary cache access. This feature reduces or increases the frequency the system
prefetches data. The options are [8], [16], [32], [40], [48], [56], [64], [72], [80], [88],
[96], [104], [112], [120].
Extended APIC (Advanced Programmable Interrupt Controller)
Based on Intel's Hyper-Threading architecture, each logical processor (thread) is
assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-
able, the APIC ID will be expanded from 8 bits to 16 bits to provide 512 APIDs to
each thread to enhance CPU performance. The options are Disable and Enable.
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