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Supermicro X10DBT User Manual

Supermicro X10DBT User Manual

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X10DBT
X10DBT-T
USER'S MANUAL
Revision 1.0a

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Summary of Contents for Supermicro X10DBT

  • Page 1 X10DBT X10DBT-T USER’S MANUAL Revision 1.0a...
  • Page 2 This product, including software and docu- mentation, is the property of Supermicro and/or its licensors, and is supplied only under a license. Any use or reproduction of this product is not allowed, except as expressly permitted by the terms of said license.
  • Page 3 Technology, delivering the best balanced solution of performance, power efficiency, and features to address the diverse needs of next-generation data centers. With the PCH C602 built in, the X10DBT(-T) motherboard supports Integrated Clock- ing, Advanced Management Bus Infrastructure, MCTP Protocol, and Intel® Node Manager 3.0.
  • Page 4 X10DBT/X10DBT-T Motherboard User’s Manual Conventions Used in the Manual Pay special attention to the following symbols for proper system installation: Warning: Important information given to ensure proper system installation or to prevent damage to the components or injury to yourself;...
  • Page 5 Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Web Site: www.supermicro.com Europe Address: Super Micro Computer B.V. Het Sterrenbeeld 28, 5215 ML...

  • Page 6: Table Of Contents

    System health Monitoring ................1-12 ACPI Features ....................1-13 Power Supply ....................1-13 Advanced Power Management ..............1-14 Intel Intelligent Power Node Manager (NM) (Available when the "Supermicro ® Power Manager (SPM)" is Installed) ............. 1-14 Management Engine (ME) ................1-14 Chapter 2 Installation Standardized Warning Statements ..............
  • Page 7 Table of Contents Unit Identifier Switch/UID LED Indicator ..........2-19 Connecting Cables ..................2-20 Power Output Connector ................ 2-20 Fan Headers ..................... 2-21 IPMB ......................2-21 TPM/Port 80 Header ................2-22 SATA DOM Power Connectors ..............2-22 Jumper Settings .................... 2-23 Explanation of Jumpers ................
  • Page 8 X10DBT/X10DBT-T Motherboard User’s Manual Returning Merchandise for Service..............3-8 Chapter 4 BIOS Introduction ...................... 4-1 Starting BIOS Setup Utility ................4-1 How To Change the Configuration Data ............4-2 Starting the Setup Utility ................. 4-2 Main Setup ...................... 4-2 Advanced Setup Configurations..............4-4 Event Logs ....................4-45...

  • Page 9: Chapter 1 Overview

    Checklist Congratulations on purchasing your computer motherboard from an acknowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. Note 1: The X10DBT(-T) motherboard was designed to be used with a Supermicro-proprietary chassis as an integrated server platform.
  • Page 10 X10DBT/X10DBT-T Motherboard User’s Manual X10DBT(-T) Motherboard Image Note: All graphics shown in this manual were based upon the latest PCB revision available at the time of publishing of the manual. The motherboard you've received may or may not look exactly the same as the graphics...
  • Page 11 Chapter 1: Overview X10DBT(-T) Motherboard Layout COM1 LAN1 USB0/1 LAN2 UID_LED1 FAN5 SXB3 IPMI_LAN LAN CTRL +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st JBT1 Note: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/motherboard/ for details.
  • Page 12 X10DBT/X10DBT-T Motherboard User’s Manual X10DBT(-T) Quick Reference COM1 LAN1 USB0/1 LAN2 UID_LED1 FAN5 SXB3 IPMI_LAN LAN CTRL +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st...
  • Page 13 SATA DOM (Device-On-Module) power connectors 1/2 JTPM1 TPM (Trusted Platform Module)/Port 80 header LAN1/LAN2 G-bit Ethernet (GLAN) ports 1/2 (for X10DBT) 10 G-bit Ethernet (GLAN) ports 1/2 (for X10DBT-T) (IPMI)_LAN IPMI_Dedicated LAN support by the BMC NVMe8A/NVMe8B Solid-State Drive (SSD) slots for SMCI-proprietary Non-...
  • Page 14 X10DBT/X10DBT-T Motherboard User’s Manual (BP) USB 0/1 (2.0) Backpanel USB 2.0 Port 0/ Port 1 (FP) USB 2 (2.0) Front-accessible Type A USB 2.0 connection header Backpanel VGA port X10DBT(-T) LED Indicators Description State Status Standby Power LED Power On...
  • Page 15 Intel QuickPath Interconnect (QPI) links (of up to 8.0 GT/s one direction per QPI) (*E7-4800/E7-8800 CPU support is verified on some SKUs only. For the latest CPU support updates, please refer to our website at http://www.supermicro.com/prod- ucts/motherboard.) • Memory...
  • Page 16 X10DBT/X10DBT-T Motherboard User’s Manual • Network Intel i350 Gigabit (10/100/1000 Mb/s) Ethernet con- troller for LAN 1/LAN 2 ports (X10DBT only), • Intel X540 10_Gigabit Ethernet controller for LAN 1/ LAN 2 ports (X10DBT-T only) • Aspeed 2400 Baseboard Controller (BMC) supports IPMI_LAN 2.0...
  • Page 17 SuperDoctor® 5, Watch Dog, NMI • Chassis Intrusion header and detection • Dimensions 19.33" (L) x 13.68" (W) (490.98 mm x 347.47 mm) Note: For IPMI Configuration instructions, please refer to the Embedded IPMI Configuration User's Guide available @ http://www.supermicro.com/ support/manuals/.
  • Page 18 X10DBT/X10DBT-T Motherboard User’s Manual SXB3 PCIe Gen3 x8 (0-7) SXB1 PCIe Gen3 x16 PCIe Gen3 x8 (8-15) SXB4 SMI2 SMI2 CPU2 Right Socket SMI2 SMI2 PROCESSOR SMI2 SMI2 CPU1 Left Socket SMI2 SMI2 PROCESSOR PCIe Gen3 x16 BIOS 16MB SPI FLASH...

  • Page 19: Processor And Chipset Overview

    Chapter 1: Overview Processor and Chipset Overview Built upon the functionality and capability of the Intel E7-2800 v2 processors (Socket R1) and the Intel C602 PCH, the X10DBT(-T) motherboard provides the best solution for High-Performance Computing (HPC) and Cloud-computing server platforms.

  • Page 20: Special Features

    X10DBT/X10DBT-T Motherboard User’s Manual Special Features Recovery from AC Power Loss The Basic I/O System (BIOS) provides a setting that determines how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must press the power switch to turn it back on), or for it to automatically return to the power-on state.

  • Page 21: Acpi Features

    As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates. The X10DBT(-T) motherboard accommodates Supermicro-proprietary power sup- ply. For adequate cooling, be sure to use the power supply recommended for this motherboard by Supermicro.

  • Page 22: Advanced Power Management

    Intel Intelligent Power Node Manager (NM) (Available ® when the "Supermicro Power Manager (SPM)" is Installed) The Intel Intelligent Power Node Manager 3.0 (IPNM) provides your system with ® real-time thermal control and power management for maximum energy efficiency.

  • Page 23: Chapter 2 Installation

    The following statements are industry-standard warnings, provided to warn the user of situations which have the potential for bodily injury. Should you have questions or experience difficulty, contact Supermicro's Technical Support department for assis- tance. Only certified technicians should attempt to install or configure components.
  • Page 24 X10DBT/X10DBT-T Motherboard User’s Manual Attention Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les piles usagées conformément aux instructions du fabricant. ¡Advertencia! Existe peligro de explosión si la batería se reemplaza de manera incorrecta.

  • Page 25: Product Disposal

    Chapter 2: Installation Product Disposal Warning! Ultimate disposal of this product should be handled according to all national laws and regulations. 製品の廃棄 この製品を廃棄処分する場合、 国の関係する全ての法律 ・ 条例に従い処理する必要が あります。 警告 本 品的 处理 根据所有国家的法律和 章 行。 警告 本產品的廢棄處理應根據所有國家的法律和規章進行。 Warnung Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des Landes erfolgen.

  • Page 26: Static-Sensitive Devices

    X10DBT/X10DBT-T Motherboard User’s Manual ‫القىانين واللىائح الىطنية‬ ‫جميع‬ ‫وفقا ل‬ ‫ينبغي التعامل معه‬ ‫هذا المنتج‬ ‫من‬ ‫التخلص النهائي‬ ‫عند‬ 경고! 이 제품은 해당 국가의 관련 법규 및 규정에 따라 폐기되어야 합니다. Waarschuwing De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming met alle nationale wetten en reglementen.

  • Page 27: Processor And Heatsink Installation

    CPU socket cap is in place and none of the socket pins are bent; otherwise, contact your retailer immediately. Refer to the Supermicro website for updates on CPU support. Installing the E7-2800/E7-4800*/E7-8800* Series Processor (*E7-4800/E7-8800 CPU support is verified on some SKUs only. Please refer to our website for the latest CPU support updates.)
  • Page 28 X10DBT/X10DBT-T Motherboard User’s Manual 2. Press the second load lever labeled 'Close 1st' to release the load plate that covers the CPU socket from its locking position. Pull lever away from Press down on Load the socket Lever 'Close 1st' 3.
  • Page 29 Chapter 2: Installation 1. Use your thumb and the index finger to loosen the lever and open the load plate. 2. Using your thumb and index finger, hold the CPU on its edges. Align the CPU keys, which are semi-circle cutouts, against the socket keys. Socket Keys CPU Keys 3.
  • Page 30 X10DBT/X10DBT-T Motherboard User’s Manual 4. With the CPU inside the socket, inspect the four corners of the CPU to make sure that the CPU is properly installed. Gently close Push down and lock the the load plate. lever labelled 'Close 1st'.

  • Page 31: Installing A Passive Cpu Heatsink

    Chapter 2: Installation Installing a Passive CPU Heatsink 1. Do not apply any thermal grease to the heatsink or the CPU die -- the re- quired amount has already been applied. 2. Place the heatsink on top of the CPU so that the four mounting holes are aligned with those on the Motherboard and the Heatsink Bracket underneath.

  • Page 32: Removing The Heatsink

    X10DBT/X10DBT-T Motherboard User’s Manual Removing the Heatsink Warning: We do not recommend that the CPU or the heatsink be removed. However, if you do need to uninstall the heatsink, please follow the instructions below to uninstall the heatsink to prevent damage done to the CPU or the CPU socket.

  • Page 33: Installing And Removing The Memory Modules

    Chapter 2: Installation Installing and Removing the Memory Modules Note: Check Supermicro's website for recommended memory modules. CAUTION Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. Installing & Removing DIMMs 1. Insert the desired number of DIMMs into the memory slots, starting with P1M1-DIMMA1.
  • Page 34 X10DBT/X10DBT-T Motherboard User’s Manual Memory Support for the X10DBT(-T) Motherboard The X10DBT(-T) Motherboard supports Up to 1 TB of Registered (RDIMM) or up to 2 TB of Load Reduced (LRDIMM) DDR3 ECC 800/1066/1333/1600 MHz 240-pin memory modules in 32 slots (2 DIMMs per channel). For the latest memory updates, please refer to our website a at http://www.supermicro.com/products/motherboard.
  • Page 35 Chapter 2: Installation Performance Mode (2:1) - DDR3 RDIMM + LRDIMM Configuration RDIMM/LRDIMM DDR3 ECC in Performance Mode (2:1) Max Speed (GHz) ; Voltage (V); Ranks Per DIMM Slot Per Channel (SPC) and DIMM Per Channel (DPC) and Data Width (x8 is supported Max DIMM for RDIMMs but...

  • Page 36: Motherboard Installation

    X10DBT/X10DBT-T Motherboard User’s Manual Motherboard Installation All motherboards have standard mounting holes to fit different types of chassis. Make sure that the locations of all the mounting holes for both motherboard and chassis match. Although a chassis may have both plastic and metal mounting fas- teners, metal ones are highly recommended because they ground the motherboard to the chassis.

  • Page 37: Installing The Motherboard

    Chapter 2: Installation Installing the Motherboard 1. Install the I/O shield into the chassis. 2. Locate the mounting holes on the motherboard. 3. Locate the matching mounting holes on the chassis. Align the mounting holes on the motherboard against the mounting holes on the chassis. 4.

  • Page 38: Control Panel Connectors And I/O Ports

    LICENSE MEGERAC LICENSE Back Panel I/O Port Locations and Definitions 1. Gigabit_LAN 1 (X10DBT), 10G_LAN 1 (X10DBT-T) 2. Gigabit_LAN 2 (X10DBT), 10G_LAN 2 (X10DBT-T) 3. Back Panel USB 2.0 Port 0 4. Back Panel USB 2.0 Port 1 5. IPMI_Dedicated LAN 6.

  • Page 39: Video Connection

    LED Indicator Section for LAN LED TD3+ Ground information. TD3- Ground (NC: No Connection) 1. VGA 2. LAN1 (10G-LAN for X10DBT-T, GLAN for X10DBT) 3. LAN2 (10G-LAN for X10DBT-T, GLAN for X10DBT) 4. IPMI_LAN (GLAN for X10DBT(-T) X10DBT-(T) Rev. 1.02 BIOS...

  • Page 40: Universal Serial Bus (Usb)

    X10DBT/X10DBT-T Motherboard User’s Manual Universal Serial Bus (USB) Back Panel USB 0/1 (2.0) Pin Definitions Two USB2.0 ports (USB 0/1) are located Pin# Definition Pin# Definition on the I/O backpanel. In addition, a Type A USB header, located next to CPU Socket...

  • Page 41: Unit Identifier Switch/Uid Led Indicator

    Note: UID can also be triggered via IPMI on the motherboard. For more information on IPMI, please refer to the IPMI User's Guide posted on our website @http://www.super- micro.com. 1. UID Switch 2. Rear UID LED X10DBT-(T) Rev. 1.02 BIOS LICENSE MEGERAC LICENSE 2-19...

  • Page 42: Connecting Cables

    X10DBT/X10DBT-T Motherboard User’s Manual Connecting Cables Power Output Connector This motherboard supports SMCI- \proprietary power supply. A 4-pin +12V power output connector located at JPW1 on the motherboard. Be sure to use the power supply recommended for this motherboard for adequate power supply to your sys- tem.

  • Page 43: Fan Headers

    USB0/1 LAN2 UID_LED1 A. Fan 5 FAN5 SXB3 IPMI_LAN B. Fan 6 LAN CTRL C. IPMB +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st JBT1 2-21...

  • Page 44: Tpm/Port 80 Header

    X10DBT/X10DBT-T Motherboard User’s Manual TPM/Port 80 Header TPM/Port 80 Header Pin Definitions A Trusted Platform Module/Port 80 Pin # Definition Pin # Definition header, located at JTPM1, provides LCLK TPM support and Port 80 connection. LFRAME# <(KEY)> Use this header to enhance system...

  • Page 45: Jumper Settings

    Jumper Setting Definition JPL1 enables or disables Gigabit_LAN Enabled (default) ports 1/2 on the X10DBT, and 10G_LAN Disabled ports 1/2 on the X10DBT-T. See the table on the right for jumper settings. The de- fault setting is Enabled. A. GLAN1/2 Enable COM1...

  • Page 46: Cmos Clear

    X10DBT/X10DBT-T Motherboard User’s Manual CMOS Clear JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads to prevent accidental clearing of CMOS. To clear CMOS, use a metal object such as a small screwdriver to touch both pads at the same time to short the connection.

  • Page 47: Vga Enable

    VGA Enabled COM1 LAN1 USB0/1 LAN2 UID_LED1 BMC Enabled FAN5 SXB3 IPMI_LAN LAN CTRL +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st JBT1 2-25...

  • Page 48: I 2 C Bus To Pci-Exp. Slots

    X10DBT/X10DBT-T Motherboard User’s Manual C Bus to PCI-Exp. Slots C for PCI-E slots Jumper Settings Use Jumpers JI C1 and JI C2 to connect Jumper Setting Definition the System Management Bus (I C) to Pins 1-2 Normal (Default) PCI-Express slots to improve PCI per-...

  • Page 49: Manufacturer Mode Select

    See the table on the right for pin definitions. JPME1 COM1 LAN1 USB0/1 LAN2 JPME2 UID_LED1 FAN5 SXB3 IPMI_LAN LAN CTRL +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st JBT1 2-27...

  • Page 50: Onboard Led Indicators

    X10DBT/X10DBT-T Motherboard User’s Manual Onboard LED Indicators LAN 1/2 Link LED Activity LED LAN LEDs The LAN ports are located on the IO Back- Rear View (when facing the rear side of the chassis) plane on the motherboard. Each Ethernet GLAN Activity Indicator (Left) LAN port has two LEDs.

  • Page 51: Onboard Power Led

    A. PWR LED COM1 LAN1 USB0/1 LAN2 UID_LED1 B. BMC LED FAN5 SXB3 IPMI_LAN LAN CTRL +12V PWR OUTPUT JPW1 JI2C2 JI2C1 X10DBT-(T) Rev. 1.02 CLOSE 1st BIOS CLOSE 1st LICENSE CPU2 CPU1 MEGERAC LICENSE OPEN 1st OPEN 1st JBT1 2-29...

  • Page 52: 2-10 Sata Connections

    X10DBT/X10DBT-T Motherboard User’s Manual 2-10 SATA Connections SATA 2.0/3.0 Ports SATA 3.0 (I-SATA 4/5) Pin Definitions Ten SATA 2.0/3.0 connections supported by Intel Pin# Signal PCH 602 are located on the motherboard. Two Ground SATA 3.0 ports are located at I-SATA 4/5. Two SATA_TXP SATA 3.0 connections and six SATA 2.0 connec-...

  • Page 53: Chapter 3 Troubleshooting

    Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the "Technical Support Procedures" and/or "Returning Merchandise for Service" section(s) in this chapter. Note: Always disconnect the power cord before adding, changing or install- ing any hardware components.

  • Page 54: No Video

    X10DBT/X10DBT-T Motherboard User’s Manual No Video 1. If the power is on, but you have no video, remove all the add-on cards and cables. 2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for details on beep codes.

  • Page 55: Memory Errors

    2. Memory support: Make sure that the memory modules are supported by test- ing the modules using memtest86 or a similar utility. Note: Refer to the product page on our website http:\\www.supermicro. com for memory and CPU support and updates.

  • Page 56: Technical Support Procedures

    Technical Support Procedures Before contacting Technical Support, please take the following steps. Also, please note that as a motherboard manufacturer, Supermicro also sells motherboards through its channels, so it is best to first check with your distributor or reseller for...
  • Page 57 1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter or see the FAQs on our website (http://www.supermicro.com/) before contacting Technical Support. 2. BIOS upgrades can be downloaded from our website (http://www.supermicro.

  • Page 58: Battery Removal And Installation

    X10DBT/X10DBT-T Motherboard User’s Manual Battery Removal and Installation Battery Removal To remove the onboard battery, follow the steps below: 1. Power off your system and unplug your power cable. 2. Locate the onboard battery as shown below. 3. Using a tool such as a pen or a small screwdriver, push the battery lock out- wards to unlock it.

  • Page 59: Frequently Asked Questions

    Note : The SPI BIOS chip used on this motherboard cannot be removed. Send your motherboard back to our RMA Department at Supermicro for repair. For BIOS Recovery instructions, please refer to the AMI BIOS Recovery Instructions posted at http://www.supermicro.com.

  • Page 60: Returning Merchandise For Service

    X10DBT/X10DBT-T Motherboard User’s Manual Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your ven- dor for a Returned Merchandise Authorization (RMA) number. When returning the...

  • Page 61: Chapter 4 Bios

    BIOS Introduction This chapter describes the AMI BIOS setup utility for the X10DBT/X10DBT-T. It also provides the instructions on how to navigate the AMI BIOS setup utility screens. The AMI ROM BIOS is stored in a Flash EEPROM and can be easily updated.

  • Page 62: How To Change The Configuration Data

    <Delete> at the appropriate time during system boot. Note: For AMI UEFI BIOS Recovery, please refer to the UEFI BIOS Recov- ery User Guide posted @ http://www.supermicro.com/support/manuals/. Starting the Setup Utility Normally, the only visible Power-On Self-Test (POST) routine is the memory test.
  • Page 63 The date must be entered in Day MM/DD/YYYY format. The time is entered in HH:MM:SS format. (Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00.). Supermicro X10DBT Version This item displays the SMC version of the BIOS ROM used in this system.

  • Page 64: Advanced Setup Configurations

    X10DBT/X10DBT-T User’s Manual Advanced Setup Configurations Select the Advanced tab to access the following submenu items. Boot Features Boot Configuration Quiet Boot Use this item to select bootup screen display between POST messages and the OEM logo. Select Disabled to display the POST messages. Select Enabled to display the OEM logo instead of the normal POST messages.
  • Page 65 Chapter 4: AMI BIOS Wait For 'F1' If Error Select Enabled to force the system to wait until the 'F1' key is pressed when an error occurs. The options are Disabled and Enabled. Interrupt 19 Capture Interrupt 19 is the software interrupt that handles the boot disk function. When this item is set to Immediate, the BIOS ROM of the host adaptors will immediately capture Interrupt 19 at bootup and allow the drives that are attached to these host adaptors to function as bootable disks.
  • Page 66 X10DBT/X10DBT-T User’s Manual Processor 0/Processor 1  This submenu displays the following information of the CPU installed a CPU socket detected by the BIOS. • Processor Socket • Processor ID • Processor Frequency • Microcode Revision • L1 Cache RAM •...
  • Page 67 Chapter 4: AMI BIOS Execute-Disable Bit (Available if supported by the OS & the CPU) Select Enable to support Intel® Execute Disable Bit Technology, which will allow the processor to designate areas in the system memory where an application code can be executed and where it cannot, thus preventing a worm or a virus from flooding illegal codes to overwhelm the processor or damage the system during an attack.
  • Page 68 X10DBT/X10DBT-T User’s Manual Adjacent Cache Prefetch (Available when supported by the CPU) Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised. Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options are Disable and Enable.
  • Page 69 Chapter 4: AMI BIOS AES-NI (New Encryption Standard-New Instructions) Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc- tions (NI) to ensure data security. The options are Enable and Disable. Down Stream PECI (Platform Environment Control Interface) Select Enable to allow the client server to interact with the host server directly to achieve better host-client communication in the PECI platform, which will result in power saving and energy use efficiency.
  • Page 70 X10DBT/X10DBT-T User’s Manual Turbo Mode Select Enabled to use the Turbo Mode to boost system performance. The options are Enable and Disable. P-state Coordination This feature is used to change the P-state (Power-Performance State) coordi- nation type. P-state is also known as "SpeedStep" for Intel processors. Select HW_ALL to change the P-state coordination type for hardware components only.
  • Page 71 Chapter 4: AMI BIOS  CPU T State Control ACPI (Advanced Configuration Power Interface) T-States Select Enable to support CPU throttling provided by the operating system to reduce power consumption. The options are Enable and Disable.  CPU Advanced PM (Power Management) Tuning ...
  • Page 72 X10DBT/X10DBT-T User’s Manual Chipset Configuration North Bridge This feature is used to configure Intel North Bridge settings. Integrated IO Configuration EV DFX (Device Function On-Hide) Features When this feature is set to Enable, the EV_DFX Lock Bits that are located on a processor will always remain clear during electric tuning.
  • Page 73 Chapter 4: AMI BIOS Link Speed Use this item to select the PCI-E link speed for the PCI-E port specified by the user. The options are GEN1 (2.5 GT/s), GEN2 (5 GT/s), and Auto. Override Max Link Width Use this feature to set the link speed for a selected PCI-E port to override the maximum link-width which was previously set by PCI-Bifurcation.
  • Page 74 X10DBT/X10DBT-T User’s Manual • PCI-E Port Link Max • PCI-E Port Link Speed PCI-E Port Select Enable to enable the PCI-E port specified by the user. The options are Auto, Enable, and Disable. PCI-E Port Link Select Disable to disable the link that is not involved in PCI training, but its CFG space is still active.
  • Page 75 Chapter 4: AMI BIOS L0s Support When this item is set to Disable, II0 will never put its transmitter in the L0s state. The options are Disable and Enable. PM ACPI Support Select Enable to generate an _HPGPE message on a PM ACPI event. Select Disable to generate an MSI message.
  • Page 76 X10DBT/X10DBT-T User’s Manual IIO1 Configuration/IIO2 Configuration/IIO3 Configuration IOU0 (II0 PCIE Port 2) This item configures the PCI-E port Bifuraction settings for a PCI-E port specified by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto. IOU1 (II0 PCIE Port 3) This item configures the PCI-E port Bifuraction settings for a PCI-E port specified by the user.
  • Page 77 Chapter 4: AMI BIOS Link Speed Use this item to select the link speed for the PCI-E port specified by the user. The options are GEN1 (2.5 GT/s), GEN2 (5 GT/s), and Auto. Override Max Link Width Use this item to set the link speed for a selected PCI-E port to override the maximum link width that was set by PCI-bifurcation.
  • Page 78 X10DBT/X10DBT-T User’s Manual Gen3 (Generation 3) Spec (Specifics) Mode Use this item to set the Specifics mode for PCI-E Generation 3 devices. The options are Auto, 0.70 July, 0.70 Sept and 071 Sept. Gen3 (Generation 3) Phase2 Mode Use this item to set the PCI-E Generation 3 Phase 2 mode. The options are Hardware Adaptive and Manual.
  • Page 79 Chapter 4: AMI BIOS Disable TPH Select Enable to de-activate TLP Processing Hint support. The options are Dis- able and Enable.  II0 Generation Configuration The following information will display: TXT DPR memory setting Use this item to set TXT DPR settings. The options are 1M DPR, 3M DPR, 64M DPR, 128M DPR, and 255M DPR.
  • Page 80 X10DBT/X10DBT-T User’s Manual Interrupt Remapping Select Enable to support Interrupt Remapping to enhance system performance. The options are Enable and Disable. Pass Through DMA Select Enable for the Non-Iscoh VT-d engine to pass through DMA (Direct Memo- ry Access) to enhance system performance. The options are Enable and Disable.
  • Page 81 Chapter 4: AMI BIOS • LInk Speed • Current QPI Link Frequency • QPI Global MMIO Low Base/Limit • QPI Global MMIO High Base/Limit • QPI PCI-E Configuration Base/Siz (Size) Link Speed Mode Use this feature to select the data transfer speed for QPI Link connections. The options are Fast and Slow.
  • Page 82 X10DBT/X10DBT-T User’s Manual Resource Auto Adjust Select Enable for the PCI resource-requests for each CPU socket to be auto- matically adjusted on the need-base when the PCI resource allocator fails. The options are Enable and Disable. QPI Per Socket Configuration CPU 0/CPU 1...
  • Page 83 Chapter 4: AMI BIOS DDR Voltage Level Select Auto for the BIOS to set the voltage settings for all DDR3 memory mod- ules. Select Force to 1.50V to force all DDR3 memory modules to operate at 1.50V. The options are Auto and Force to 1.50V. Advanced Clk (Clock) Training Select Enable to support Advanced Clock Training, which will allow the memory command line to be synchronized with the clock line to enhance memory per-...
  • Page 84 X10DBT/X10DBT-T User’s Manual Phase Shedding Select Enabled to enable Static Phase-Shedding support for DDR3 memory voltage regulators to improve memory performance. The options are Auto, Disabled and Enabled. Multi-Threaded MRC (Memory Reference Code) Select Enabled for the system to execute multi-threaded memory codes to improve memory performance.
  • Page 85 Chapter 4: AMI BIOS Enable ADR Select Enabled for ADR (Automatic Diagnostic Repository) support to enhance memory performance. The options are Enabled and Disabled. VMSE Lockstep Mode Select Enabled to support the VMSE Lockstep mode, which will support Lock step mode for the Intel Scalable Memory Interconnect 2 (Intel SMI 2) controller. The options are 2:1 Mode.
  • Page 86 X10DBT/X10DBT-T User’s Manual Unused Memory Channel Input Select Enabled to allow input from unused memory channels. The options are Enabled and Disabled. Command 2 Data Tuning Select Enabled to fine-tune electrical command paths from the host system to the memory-extension buffer (MXB). The options are Enabled and Disabled.
  • Page 87 Chapter 4: AMI BIOS Closed Loop Thermal Throttling Select Enabled to support Closed-Loop Thermal Throttling which will improve reliability and reduces CPU power consumption via automatic voltage control while the CPU are in idle states. The options are Disabled and Enabled. Memory Hot Sense Thermal Throttling Select Enabled to activate thermal-throttling when the hot-sensor reaches the predefined threshold via automatic voltage control when the CPU is in idle states.
  • Page 88 X10DBT/X10DBT-T User’s Manual Memory Topology This item displays the status of each DIMM module as detected by the BIOS. • Node • Channel • DIMM Frequency Memory Thermal Memory Power Savings Mode Use this item to configure chipset-related memory power-saving features. The options are Auto, Slow, Fast, Disabled, and User Defined.
  • Page 89 Chapter 4: AMI BIOS Memory Frequency Use this item to set the frequency of system memory. The options are Auto, 1067 (MHz), 1333 (MHz), 1600 (MHz), 1867 (MHz), 2133 (MHz), and 2400 (MHz). Memory RAS (Reliability_Availability_Serviceability) Configuration Use this submenu to configure the following Memory RAS settings. Memory RAS Configuration Setup Socket 0 Branch 0/Socket 0 Branch1/Socket 1 Branch 0/Socket 1 Branch1 Select Enable to enable the memory module installed on the socket specified by...
  • Page 90 X10DBT/X10DBT-T User’s Manual Leaky Bucket High Bit Use this feature to set the High Bit value for the Leaky Bucket algorithm which is used to check the data transmissions between CPU sockets and the memory controller. The default setting is 41.
  • Page 91 Chapter 4: AMI BIOS Demand Scrub Demand Scrubbing is a process that allows the CPU to correct correctable memory errors found on a memory module. When the CPU or I/O issues a demand-read command, and the read data from memory turns out to be a correctable error, the error is corrected and sent to the requestor (the original source).
  • Page 92 X10DBT/X10DBT-T User’s Manual Apply Memory RAS Policy Globally Select Enable to apply Memory RAS policy to all related components and systems. The options are Disable and Enable. Memory Mirroring Select Enable to enable memory-mirroring support which will create a duplicate copy of the data stored in the memory to enhance data security.
  • Page 93 Chapter 4: AMI BIOS Port 60/64 Emulation Select Enabled for I/O port 60h/64h emulation support which will provide complete USB keyboard legacy support for the operating system that does not support Legacy USB devices. The options are Disabled and Enabled. USB Hardware Delays and Time-outs USB Transfer Time-out Use this feature sets the USB Transfer Time-out values for control, bulk, and inter-...
  • Page 94 X10DBT/X10DBT-T User’s Manual Support Aggressive Link Power Management When this item is set to Enabled, the SATA AHCI controller manages the power usage of the SATA link. The controller will put the link in a low power mode during extended periods of I/O inactivity, and will return the link to an active state when I/O activity resumes.
  • Page 95 Chapter 4: AMI BIOS *If the item above "Configure SATA as" is set to RAID, the following items will display: Support Aggressive Link Power Management When this item is set to Enabled, the SATA AHCI controller manages the power usage of the SATA link. The controller will put the link in a low power mode during extended periods of I/O inactivity, and will return the link to an active state when I/O activity resumes.
  • Page 96 X10DBT/X10DBT-T User’s Manual SCU (Storage Control Unit) Configuration Storage Controller Unit Select Enabled to enable PCH SCU storage devices. The options are Disable and Enable. Onchip SCU Option ROM Select Disabled to boot the system from a SAS device. Select EFI to boot the system from an EFI device.
  • Page 97 Chapter 4: AMI BIOS SERR# Generation Select Enabled to allow a PCI/PCI-E device to generate a System-Error (SERR) number for a PCI Bus Signal Error Event. The options are Enabled and Disabled. PCI AER (Advanced Error-Reporting) Support Select Enabled to support Advanced Error-Reporting for onboard PCI devices. The options are Disabled and Enabled.
  • Page 98 X10DBT/X10DBT-T User’s Manual PCI Devices Option ROM Settiing Slot1 x16 thru (through) SXB1 OPROM/Slot2 x16 thru (through) SXB1 OPROM/Slot SXB2 x8 thru (through) BPN-ADP-8SATA3-1 OPROM/Slot SXB3 x8 OPROM Use this feature to select the type of device installed on a slot specified by the user for the system to boot from.
  • Page 99 Chapter 4: AMI BIOS • ME Firmware Status #1 • ME Firmware Status #2 • Current State • Error Code Super IO Configuration Super IO Chip: This item displays the Super IO chip used in the motherboard. Serial Port 1 Configuration Serial Port Select Enabled to enable a serial port specified by the user.
  • Page 100 X10DBT/X10DBT-T User’s Manual Change Settings This option specifies the base I/O port address and the Interrupt Request address of Serial Port 2 (SOL). Select Disabled to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port becomes unavailable.
  • Page 101 Chapter 4: AMI BIOS add color and function key support. Select ANSI to use the Extended ASCII Char- acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8. Bits Per second Use this feature to set the transmission speed for a serial port used in Console Redirection.
  • Page 102 X10DBT/X10DBT-T User’s Manual Resolution 100x31 Select Enabled for extended-terminal resolution support. The options are Dis- abled and Enabled. Legacy OS Redirection Resolution Use this feature to select the number of rows and columns used in Console Redirection for legacy OS support. The options are 80x24 and 80x25.
  • Page 103 Chapter 4: AMI BIOS character set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8. Bits Per Second This item sets the transmission speed for a serial port used in Console Redirec- tion.
  • Page 104 X10DBT/X10DBT-T User’s Manual TPM Enable Status This item displays the status of TPM Support to indicate if TPM is currently enabled or disabled. TPM Active Status This item displays the status of TPM Support to indicate if TPM is currently ac- tive or deactivated.
  • Page 105 Chapter 4: AMI BIOS Event Logs Select the Event Logs tab to access the following submenu items. Change SMBIOS Event Log Settings  This feature allows the user to configure SMBIOS Event settings. Runtime Error Logging Support Select Enabled to enable runtime error logging upon system boot. The options are Auto, Enabled, and Disabled.
  • Page 106 X10DBT/X10DBT-T User’s Manual SMBIOS Event Log Standard Settings Log System Boot Event Select Enabled to log system boot events. The options are Disabled and Enabled. MECI (Multiple Event Count Increment) Enter the increment value for the multiple event counter. Enter a number from 1 to 255.
  • Page 107 Chapter 4: AMI BIOS IPMI Select the IPMI (Intelligent Platform Management Interface) tab to access the fol- lowing submenu items. These items indicates your system IPMI firmware revision number and status. • IPMI Firmware Revision • IPMI Status BMC Network Configuration ...
  • Page 108 X10DBT/X10DBT-T User’s Manual Station IP Address (Available when the item above is set to Yes) This item displays the Station IP address for this computer. This should be in decimal and in dotted quad form (i.e., 192.168.10.253). Subnet Mask (Available when the item above is set to Yes) This item displays the sub-network that this computer belongs to.
  • Page 109 Chapter 4: AMI BIOS Security This menu allows the user to configure the following security settings for the system. Administrator Password Use this item to set the administrator password which is required to enter the BIOS setup utility. The length of the password should be from 3 characters to 20 characters long.
  • Page 110 X10DBT/X10DBT-T User’s Manual Boot This submenu allows the user to configure the following boot settings for the system. Boot Mood Select Use this item to configure boot mood select settings for the machine. The options are Legacy, UEFI, and Dual.
  • Page 111 Chapter 4: AMI BIOS  Hard Disk Drive BBS Priorities (Available when a device is installed in this drive) This item sets the boot sequence of available hard disk drives. • Boot Order #1  CD/DVD ROM Drive BBS Priorities (Available when a device is installed in this drive) •...
  • Page 112 X10DBT/X10DBT-T User’s Manual Save & Exit This submenu allows the user to configure the Save and Exit settings for the system. Save Changes and Exit When completing the system configuration changes, select this option to save the changes and exit from the BIOS setup utility. When a dialog box appears, asking you if you want to save configuration and exit, select Yes to save the changes and exit from the BIOS setup utility.
  • Page 113 Chapter 4: AMI BIOS Save Options Save Changes Select this option and press <Enter> to save all changes you've made so far and return to the AMI BIOS utility. When the dialog box appears, asking you if you want to save configuration, select Yes to save the changes, or select No to return to the BIOS without making changes.
  • Page 114 X10DBT/X10DBT-T User’s Manual Notes 4-54...
  • Page 115 Appendix A: BIOS POST Error Codes Appendix A BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed at each system boot, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue to boot.
  • Page 116 X10DBT/X10DBT-T Motherboard User’s Manual Notes...
  • Page 117 Appendix B Software Installation Instructions B-1 Installing Software Programs The Supermicro website that contains drivers and utilities for your system is located at http://www.supermicro.com/wftp. Some of these must be installed, such as the chipset driver. After accessing the product drivers and utilities page, go into the CDR_Images directory and locate the ISO file for your motherboard.
  • Page 118 B-2 Configuring SuperDoctor 5 The Supermicro SuperDoctor 5 is a hardware monitoring program that functions in a command-line or web-based interface in Windows and Linux operating systems. The program monitors system health information such as CPU temperature, system voltages, system power consumption, fan speed, and provides alerts via email or Simple Network Management Protocol (SNMP).
  • Page 119 Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall Supermicro be liable for direct, indirect, special, incidental, or consequential damages arising from a BIOS update. If you need to update the BIOS, do not shut down or reset the system while the BIOS is updating to avoid possible boot failure.
  • Page 120 Root "\" Directory of a USB device or a writeable CD/DVD. Note: If you cannot locate the "Super.ROM" file in your driver disk, visit our website at www.supermicro.com to download the BIOS image into a USB flash device and rename it "Super ROM" for BIOS recovery use.
  • Page 121 Appendix C: UEFI BIOS Recovery 6. After the process of BIOS Recovery is complete, press any key to reboot the system. 7. Using a different system, extract the BIOS package into a bootable USB flash drive. 8. When a DOS prompt appears, enter AMI.BAT BIOSname.### at the prompt. Note: Do not interrupt this process until BIOS flashing is completed.
  • Page 122 X10DBT/X10DBT-T Motherboard User’s Manual 9. After seeing the message that BIOS update is completed, unplug the AC pow- er cable from the power supply to clear CMOS, and then plug the AC power cable in the power supply again to power on the system.

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