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Summary of Contents for Texas Instruments TMS320DM644x
- Page 1 TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide Literature Number: SPRUE30B September 2006...
- Page 2 SPRUE30B – September 2006 Submit Documentation Feedback...
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Page 3: Table Of Contents
Preface Introduction Purpose of the Peripheral Features Functional Block Diagram Supported Use Case Statement Industry Standard(s) Compliance Statement Peripheral Architecture Clock Control Signal Descriptions Protocol Descriptions Data Flow in the Input/Output FIFO Data Flow in the Data Registers (MMCDRR and MMCDXR) FIFO Operation During Card Read Operation FIFO Operation During Card Write Operation Reset Considerations... - Page 4 4.13 MMC Command Register (MMCCMD) 4.14 MMC Argument Register (MMCARGHL) 4.15 MMC Response Registers (MMCRSP0-MMCRSP7) 4.16 MMC Data Response Register (MMCDRSP) 4.17 MMC Command Index Register (MMCCIDX) 4.18 MMC FIFO Control Register (MMCFIFOCTL) Appendix A Revision History Contents SPRUE30B – September 2006 Submit Documentation Feedback...
- Page 5 MMC/SD Card Controller Block Diagram MMC/SD Controller Interface Diagram MMC Configuration and SD Configuration Diagram MMC/SD Controller Clocking Diagram MMC/SD Mode Write Sequence Timing Diagram MMC/SD Mode Read Sequence Timing Diagram FIFO Operation Diagram Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA FIFO Operation During Card Read Diagram FIFO Operation During Card Write Diagram...
- Page 6 MMC/SD Controller Pins Used in Each Mode MMC/SD Mode Write Sequence MMC/SD Mode Read Sequence Description of MMC/SD Interrupt Requests Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers MMC Control Register (MMCCTL) Field Descriptions MMC Memory Clock Control Register (MMCCLK) Field Descriptions MMC Status Register 0 (MMCST0) Field Descriptions MMC Status Register 1 (MMCST1) Field Descriptions MMC Interrupt Mask Register (MMCIM) Field Descriptions...
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Page 7: Preface
This manual describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards. - Page 8 SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.
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Page 9: Introduction
Multimedia Card (MMC)/Secure Digital (SD) Card Introduction This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). Purpose of the Peripheral A number of applications use the multimedia card (MMC)/secure digital (SD) card to provide removable data storage. -
Page 10: Supported Use Case Statement
Peripheral Architecture Figure 1. MMC/SD Card Controller Block Diagram ARM CPU DMA requests Interrupts Supported Use Case Statement The MMC/SD card controller supports the following user cases: MMC/SD card identification MMC/SD single-block read using CPU MMC/SD single-block read using EDMA MMC/SD single-block write using CPU MMC/SD single-block write using EDMA MMC/SD multiple-block read using CPU... -
Page 11: Mmc/Sd Controller Interface Diagram
www.ti.com Figure 2. MMC/SD Controller Interface Diagram Memory EDMA Figure 3. MMC Configuration and SD Configuration Diagram MMC/SD controller MMC/SD controller SPRUE30B – September 2006 Submit Documentation Feedback MMCs or SD cards MMC/SD controller Native packets DAT0 or DAT0−3 MMC/SD configuration MMC and SD (1−bit mode) SD_CLK SD_CMD... -
Page 12: Clock Control
Peripheral Architecture Clock Control There are two clocks, the function clock and the memory clock, in the MMC/SD controller The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD card(s). The MMC/SD controller is capable of operating with a function clock up to 100 MHz. -
Page 13: Signal Descriptions
www.ti.com Signal Descriptions Table 1 shows the MMC/SD controller pins that each mode uses. The MMC/SD protocol uses the clock, command (two-way communication between the MMC controller and memory card), and data (DAT0 for MMC card, DAT0-3 for SD card) pins. Table 1. -
Page 14: Mmc/Sd Mode Write Sequence Timing Diagram
Peripheral Architecture Figure 5. MMC/SD Mode Write Sequence Timing Diagram Data Portion of the Sequence Description WR CMD Write command: A 6-byte WRITE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a 6-byte response of type R1 to acknowledge the WRITE_BLOCK to the ARM. -
Page 15: Data Flow In The Input/Output Fifo
www.ti.com Figure 6. MMC/SD Mode Read Sequence Timing Diagram Data Portion of the Sequence Description RD CMD Read command: A 6-byte READ_SINGLE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a response of type R1 to acknowledge the READ_SINGLE_BLOCK command to the ARM. -
Page 16: Fifo Operation Diagram
Peripheral Architecture A high-level operational description is as follows: Data is written to the FIFO through the MMC data transmit register (MMCDXR). Data is read from the FIFO through the MMC data receive register (MMCDRR). This is true for both the CPU and EDMA driven transactions;... -
Page 17: Data Flow In The Data Registers (Mmcdrr And Mmcdxr)
www.ti.com Data Flow in the Data Registers (MMCDRR and MMCDXR) The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register (MMCDRR) and write 32 bits at a time to the FIFO by writing to the MMC data transmit register (MMCDXR). -
Page 18: Big-Endian Access To Mmcdxr/Mmcdrr From The Arm Cpu Or The Edma
Peripheral Architecture Figure 9. Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA Multimedia Card (MMC)/Secure Digital (SD) Card Controller Support byten = ”1111” Support byten = ”1110” Support byten = ”1100” Support byten = ”1000” www.ti.com SPRUE30B – September 2006 Submit Documentation Feedback... -
Page 19: Fifo Operation During Card Read Operation
www.ti.com FIFO Operation During Card Read Operation 2.6.1 EDMA Reads The FIFO controller manages the activities of reading the data in from the card and issuing EDMA read events. Each time an EDMA read event is issued, an EDMA read request interrupt generates. Figure 10 provides details of the FIFO controllers operation. -
Page 20: Fifo Operation During Card Read Diagram
Peripheral Architecture Figure 10. FIFO Operation During Card Read Diagram FIFO Check1/Start no DMA pending Increment counter Increment counter Multimedia Card (MMC)/Secure Digital (SD) Card Controller FIFO full Capture data, Counter =FIFOLEV Generate DMA Reset counter FIFO check 2 FIFO full Capture data, Counter... -
Page 21: Fifo Operation During Card Write Operation
www.ti.com FIFO Operation During Card Write Operation 2.7.1 EDMA Writes The FIFO controller manages the activities of accepting data from the CPU or EDMA and passing the data to the MMC/SD controller. The FIFO controller issues EDMA write events as appropriate. Each time an EDMA write event is issued, an EDMA write request interrupt generates. -
Page 22: Fifo Operation During Card Write Diagram
Peripheral Architecture Figure 11. FIFO Operation During Card Write Diagram FIFO Check1/Start no DMA pending Increment counter Increment counter Multimedia Card (MMC)/Secure Digital (SD) Card Controller FIFO full Capture data, Counter =FIFOLEV Generate DMA Reset counter FIFO check 2 FIFO full Capture data, Counter... -
Page 23: Reset Considerations
www.ti.com Reset Considerations The MMC/SD peripheral has two reset sources: hardware reset and software reset. 2.8.1 Software Reset Considerations A software reset (such as a reset that the emulator generates) does not cause the MMC/SD controller registers to alter. After a software reset, the MMC/SD controller continues to operate as it was configured prior to the reset. - Page 24 Peripheral Architecture 2.9.3 Initializing the Clock Controller Registers (MMCCLK) A clock divider in the MMC/SD controller divides-down the function clock to produce the memory clock. Load the divide-down value into the CLKRT bits in the MMC memory clock control register (MMCCLK). The divide-down value is determined by the following equation: memory clock frequency = function clock frequency/(2 ×...
- Page 25 www.ti.com 2.9.7 Monitoring Activity in the MMC/SD Mode This section describes registers and specific register bits that you can use to obtain the status of the MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1).
- Page 26 Peripheral Architecture 2.9.7.8 Determining When Last Data has Been Written to Card (SanDisk SD cards) Some SanDisk brand SD™ cards exhibit a behavior that requires a multiple-block write command to terminate with a STOP (CMD12) command before the data write sequence completes. To enable support of this function, the transfer done interrupt (TRNDNE) is provided.
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Page 27: 2.10 Interrupt Support
www.ti.com 2.10 Interrupt Support 2.10.1 Interrupt Events and Requests The MMC/SD controller generates the interrupt requests described in occurs, its flag bit is set in the MMC status register 0 (MMCST0). If the enable bits corresponding to each flag are set in the MMC interrupt mask register (MMCIM), an interrupt request generates. All such requests are multiplexed to a single MMC/SD interrupt request from the MMC/SD peripheral to the ARM CPU. -
Page 28: 2.11 Dma Event Support
The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14). 2.13 Emulation Considerations The MMC/SD peripheral is not affected by emulation halt events (such as breakpoints). -
Page 29: Procedures For Common Operations
www.ti.com Procedures for Common Operations Card Identification Operation Before the MMC/SD controller starts data transfers to or from memory cards in the MMC/SD native mode, it must first identify how many cards are present on the bus and configure them. For each card that responds to the ALL_SEND_CID broadcast command, the controller reads that card’s unique card identification address (CID) and then assigns it a relative address (RCA). -
Page 30: Mmc Card Identification Procedure
Procedures for Common Operations Figure 12. MMC Card Identification Procedure 3.1.2 SD Card Identification Procedure The SD card identification procedure is: 1. Use the MMC command register (MMCCMD) to issue the GO_IDLE_STATE (CMD0) command to the MMC cards. Using MMCMD to issue the CMD0 command puts all cards (MMC and SD) in the idle state and no response from the cards is expected. -
Page 31: Sd Card Identification Procedure
www.ti.com 6. Repeat step 4 and step 5 to identify and retrieve relative addresses from all remaining SD cards until no card responds to the CMD2 command. No card responding within 5 memory clock cycles indicates that all cards have been identified and the MMC card and the identification procedure terminates. The sequence of events in this operation is shown in Figure 13. -
Page 32: Mmc/Sd Mode Single-Block Write Operation Using Cpu
Procedures for Common Operations MMC/SD Mode Single-Block Write Operation Using CPU To perform a single-block write, the block length must be 512 bytes and the same length needs to be set in both the MMC/SD controller and the memory card. The procedure for this operation is: 1. -
Page 33: Mmc/Sd Mode Single-Block Write Operation
www.ti.com Figure 14. MMC/SD Mode Single-Block Write Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW FIRST DATA BYTE WRITE BLOCK Is CRCWR = 1? Is DATDNE = 1? Is DXRDY = 1? NEXT DATA BYTE SPRUE30B –... -
Page 34: Mmc/Sd Mode Single-Block Write Operation Using The Edma
Procedures for Common Operations MMC/SD Mode Single-Block Write Operation Using the EDMA To perform a single-block write, the block length must be 512 bytes and the same length must be set in both the MMC/SD controller and the card. The procedure for this operation is as follows: 1. -
Page 35: Mmc/Sd Mode Single-Block Read Operation Using Edma
www.ti.com Figure 15. MMC/SD Mode Single-Block Read Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_SINGLE_BLOCK Is CRCWR = 1? Is DXRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION MMC/SD Mode Single-Block Read Operation Using EDMA To perform a single-block read, the same block length needs to be set in both the MMC/SD controller and the card. -
Page 36: Mmc/Sd Mode Multiple-Block Write Operation Using Cpu
Procedures for Common Operations MMC/SD Mode Multiple-Block Write Operation Using CPU To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controller and the card. Note: The procedure in this section uses a STOP_TRANSMISSION command to end the block transfer. This assumes that the value in the MMC number of blocks counter register (MMCNBLK) is 0. -
Page 37: Mmc/Sd Multiple-Block Write Operation
www.ti.com Figure 16. MMC/SD Multiple-Block Write Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_SINGLE_BLOCK Is CRCWR = 1? Is DXRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION SPRUE30B – September 2006 Submit Documentation Feedback MMC controller register... -
Page 38: Mmc/Sd Mode Multiple-Block Write Operation Using Edma
Procedures for Common Operations MMC/SD Mode Multiple-Block Write Operation Using EDMA To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controller and the card. The procedure for this operation is: 1. Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL. -
Page 39: Mmc/Sd Mode Multiple-Block Read Operation Using Edma
www.ti.com Figure 17. MMC/SD Mode Multiple-Block Read Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_MULT_BLOCK Is TOUTRD = 1? Is CRCRD = 1? Is DRRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION MMC/SD Mode Multiple-Block Read Operation Using EDMA... -
Page 40: Registers
Registers Registers Table 5 lists the memory-mapped registers for the multimedia card/secure digital (MMC/SD) card controller. See the device-specific data manual for the memory address of these registers. Table 5. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers Offset Acronym MMCCTL MMCCLK MMCST0 MMCST1... -
Page 41: Mmc Control Register (Mmcctl)
www.ti.com MMC Control Register (MMCCTL) The MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controller. Set or clear the DATRST and CMDRST bits at the same time to reset or enable the MMC controller. The MMC control register (MMCCTL) is shown in Reserved DATEG... -
Page 42: Mmc Memory Clock Control Register (Mmcclk)
Registers MMC Memory Clock Control Register (MMCCLK) The MMC memory clock control register (MMCCLK) is used to: Select whether the CLK pin is enabled or disabled (CLKEN bit). Select how much the function clock is divided-down to produce the memory clock (CLKRT bits). When the CLK pin is enabled, the MMC controller drives the memory clock on this pin to control the timing of communications with attached memory cards. -
Page 43: Mmc Status Register 0 (Mmcst0)
www.ti.com MMC Status Register 0 (MMCST0) The MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1 on each bit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set the corresponding interrupt enable bit in the MMC interrupt mask register (MMCIM). - Page 44 Registers Table 8. MMC Status Register 0 (MMCST0) Field Descriptions (continued) Field Value Description CRCWR Write-data CRC error. A write-data CRC error has not been detected. A write-data CRC error has been detected. TOUTRS Response time-out event. A response time-out event has not occurred. A time-out event has occurred while the MMC controller was waiting for a response to a command.
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Page 45: Mmc Status Register 1 (Mmcst1)
www.ti.com MMC Status Register 1 (MMCST1) The MMC status register 1 (MMCST1) records specific events or errors. There are no interrupts associated with these events or errors. The MMC status register 1 (MMCST1) is shown in Reserved FIFOFUL FIFOEMP LEGEND: R = Read only; -n = value after reset Table 9. -
Page 46: Mmc Interrupt Mask Register (Mmcim)
Registers MMC Interrupt Mask Register (MMCIM) The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts. If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU. -
Page 47: Mmc Response Time-Out Register (Mmctor)
www.ti.com Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued) Field Value Description ETOUTRD Read-data time-out event (TOUTRD) interrupt enable. Read-data time-out event interrupt is disabled. Read-data time-out event interrupt is enabled. ERSPDNE Command/response done (RSPDNE) interrupt enable. Command/response done interrupt is disabled. Command/response done interrupt is enabled. -
Page 48: Mmc Data Read Time-Out Register (Mmctod)
Registers MMC Data Read Time-Out Register (MMCTOD) The MMC data read time-out register (MMCTOD) defines how long the MMC controller waits for the data from a memory card before recording a time-out condition in the TOUTRD bit of the MMC status register 0 (MMCST0). -
Page 49: Mmc Block Length Register (Mmcblen)
www.ti.com MMC Block Length Register (MMCBLEN) The MMC block length register (MMCBLEN) specifies the data block length in bytes. This value must match the block length setting in the memory card. The MMC block length register (MMCBLEN) is shown in Figure 25. -
Page 50: Mmc Number Of Blocks Register (Mmcnblk)
Registers MMC Number of Blocks Register (MMCNBLK) The MMC number of blocks register (MMCNBLK) specifies the number of blocks for a multiple-block transfer. The MMC number of blocks register (MMCNBLK) is shown in Figure 26. MMC Number of Blocks Register (MMCNBLK) LEGEND: R/W = Read/Write;... -
Page 51: Mmc Data Receive Register (Mmcdrr)
www.ti.com 4.11 MMC Data Receive Register (MMCDRR) The MMC data receive register (MMCDRR) is used for storing the received data from the MMC controller. The CPU or the DMA controller can read data from this register. MMCDRR expects the data in little-endian format. -
Page 52: Mmc Command Register (Mmccmd)
Registers 4.13 MMC Command Register (MMCCMD) Note: Writing to the MMC command register (MMCCMD) causes the MMC controller to send the programmed command. Therefore, the MMC argument register (MMCARGHL) must be loaded properly before a write to MMCCMD. The MMC command register (MMCCMD) specifies the type of command to be sent and defines the operation (command, response, additional activity) for the MMC controller. -
Page 53: Command Format
www.ti.com Table 18. MMC Command Register (MMCCMD) Field Descriptions (continued) Field Value Description STRMTP Stream enable. If WDATX = 1, the data transfer is a block transfer. The data transfer stops after the movement of the programmed number of bytes (defined by the programmed block size and the programmed number of blocks). -
Page 54: Mmc Argument Register (Mmcarghl)
Registers 4.14 MMC Argument Register (MMCARGHL) Note: Do not modify the MMC argument register (MMCARGHL) while it is being used for an operation. The MMC argument register (MMCARGHL) specifies the arguments to be sent with the command specified in the MMC command register (MMCCMD). Writing to MMCCMD causes the MMC controller to send a command;... -
Page 55: Mmc Response Register 0 And 1 (Mmcrsp01)
www.ti.com 4.15 MMC Response Registers (MMCRSP0-MMCRSP7) Each command has a preset response type. When the MMC controller receives a response, it is stored in some or all of the eight MMC response registers (MMCRSP7-MMCRSP0). The response registers are updated as the responses arrive, even if the CPU has not read the previous contents. As shown in Figure Figure... -
Page 56: R1, R3, R4, R5, Or R6 Response (48 Bits)
Registers Table 21. R1, R3, R4, R5, or R6 Response (48 Bits) Bit Position of Response 47-40 39-24 23-8 Bits 7-0 of the response are stored to bits 7-0 of MMCRSP5. Bit Position of Response 135-128 127-112 111-96 95-80 79-64 63-48 47-32 31-16... -
Page 57: Mmc Data Response Register (Mmcdrsp)
www.ti.com 4.16 MMC Data Response Register (MMCDRSP) After the MMC controller sends a data block to a memory card, the return byte from the memory card is stored in the MMC data response register (MMCDRSP). The MMC data response register (MMCDRSP) is shown in Figure 37. -
Page 58: Mmc Fifo Control Register (Mmcfifoctl)
Registers 4.18 MMC FIFO Control Register (MMCFIFOCTL) The MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39. MMC FIFO Control Register (MMCFIFOCTL) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions Field Value Description... -
Page 59: Appendix A Revision History
www.ti.com Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Section 1.2 Changed third bullet. Added seventh bullet. Section 1.3 Added second sentence. Section 1.5 Deleted third bullet. Section 2 Changed second sentence in second paragraph. - Page 60 www.ti.com Appendix A Revision History SPRUE30B – September 2006 Submit Documentation Feedback...
- Page 61 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
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