Motorola MVME2700 Series Installation And Use Manual page 212

MVME761 transition module
jumpers
J17 (SP4 transmit clock)
J18 (SP3 transmit clock)
J19 (SP4 clock receiver buffer)
J20 (system controller)
J9 (Flash bank selection)
jumpers, backplane
jumpers, setting 1-6,
K
keyboard/mouse interface 3-10,
L
L1 and L2 cache 1-1, 3-1,
LAN transceiver 1-62,
LED functions 2-3,
LED mezzanine 1-11, 2-3, 3-20, 3-22,
lithium battery
local reset (LRST) 2-2,
lowercase characters, use of
M
M48T59 RAM and clock chip
manufacturers' documents
memory capacities
memory maps
default processor
overview
PCI local bus
VMEbus
memory mezzanine module 1-47,
memory requirements, PPCBug
multiplexing function (P2)
MVME2700
board structure
I
connector locations
N
installation
D
power distribution
E
preparation
X
MVME712M
cable connections
IN-4
1-25
1-9
1-10
1-9
1-11
1-8
1-54
1-11
4-10
3-3
3-21
3-20
3-13
3-19
5-9
3-13
D-2
3-24
2-5
2-4
2-6
2-6
3-23
5-2
3-17
6-2
1-7
1-53
1-62
1-6
1-57
connector locations
installation
P2 adapter board
preparation
serial port configuration
MVME761
cable connections
connector locations
installation
P2 adapter board
preparation
serial port configuration
N
non-volatile RAM (NVRAM) 6-1,
NVRAM 6-1
NVRAM (BBRAM) configuration area
4-2
O
operatiang atemperature, storage tempera-
ture, humidity specifications
operating parameters
P
P2 adapter
MVME712M
MVME761 1-44,
termination
P2 multiplexing
packing instructions
parallel port 2-10, 3-2, 3-10, 3-24, 3-25, 4-23,
4-29
parameter syntax
parameters
autoboot
auto-initialize NVRAM header
boot priority
cross-loaded program
DRAM parity
DRAM speed
L2 cache parity
memory size
Computer Group Literature Center Web Site
1-13
1-55
1-22
1-12
1-14 to 1-21
1-59
1-24
1-58
1-32
1-23
1-25 to 1-31
6-3
A-1
6-1
1-22
1-45
3-7
3-17
1-5
6-2
6-6
6-4
6-6
6-4
6-11
6-10
6-12
6-10
Index
3-7