Block Diagram; Figure 1 - Block Diagram - Sundance Spas SMT370v2 User Manual

Version 1.0

Block Diagram.

The following diagram shows the architecture of the SMT370v2.
3 Power
supply
LEDs
'FPGA configured'
LED
On-board Oscillator
50 MHz
4 LEDs or
4 LVTTL I/O pins
FPGA PROM
XC18V04
6-pin JTAG
JTAG chain
header
2 Sundance High-speed
Bus connector: 2 x 60 bits
One bank of 1Mx32 bits of
NtSRAM - 166 MHz
Connections to the outside world are greyed out.
Main parts of the board are described in the next part of this document.
J2 Bottom Primary TIM
120 I/O pins
106 I/O pins; 44-bit data
2x CommPorts/SDLs 0 & 3

Figure 1 - Block Diagram.

Page 7 of 44
Connector
Trig
1
Trig
2
30 I/O pins; 28-bit data; ctl
Xilinx FPGA
Virtex-II, FG456
parameters
XC2V1000-6
324 I/O Pins
1.5V Core
3.3V I/O
44 I/O pins; 16-bit data; ctl
J1 Top Primary TIM
Connector
SMT370v2 User Manual
#1
AC or DC
coupling*
2xAD6645 ADCs
14-bit @ 105MSPS
Clock feedback
Clock
2xClock
synthesizers
Multiplexer
Clock selection
1x AD9777 DAC
16-bit @ 400MSPS
80-pin TQFP
Clock feedback
RF
transformer
#3
* Option to the board
#2
AC or DC
coupling*
52-pin LQFP
Clk
Filter
Clock
1
Clk
Filter
2
RF
transformer
#4