Register 0X5 - Clock Management - Sundance Spas SMT370v2 User Manual

Version 1.0
Register 0x5 – Clock management.
Bit number
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24 Clock Selection DAC/FPGA – must match with Bit 25 ('0'=Internal; '1'=External)
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 31 of 44
Description
Clock Selection ADCA (ADCA - '0'=Internal; '1'=External)
Clock Selection ADCB (ADCB - '0'=Internal; '1'=External)
Clock Selection DAC ('0'=Internal; '1'=External)
Clock synthesizer – N (divider) Bit2 – ADCs
Clock synthesizer – N (divider) Bit1 – ADCs
Clock synthesizer – N (divider) Bit0 – ADCs
Clock synthesizer - M Bit8 – ADCs
Clock synthesizer – M Bit7 – ADCs
Clock synthesizer - M Bit6 – ADCs
Clock synthesizer - M Bit5 – ADCs
Clock synthesizer - M Bit4 – ADCs
Clock synthesizer - M Bit3 – ADCs
Clock synthesizer - M Bit2 – ADCs
Clock synthesizer - M Bit1 – ADCs
Clock synthesizer - M Bit0 – ADCs
Clock synthesizer – N (divider) Bit2 - DAC
Clock synthesizer – N (divider) Bit1 - DAC
Clock synthesizer – N (divider) Bit0 - DAC
Clock synthesizer - M Bit8 - DAC
Clock synthesizer - M Bit7 - DAC
Clock synthesizer - M Bit6 - DAC
Clock synthesizer - M Bit5 - DAC
Clock synthesizer - M Bit4 - DAC
Clock synthesizer - M Bit3 - DAC
Clock synthesizer - M Bit2 - DAC
Clock synthesizer - M Bit1 - DAC
Clock synthesizer - M Bit0 - DAC
0
1
0
1
SMT370v2 User Manual