Architecture Description; Smt351 Block Diagram; Figure 1: Smt351 Board Block Diagram - Sundance Spas SMT351 User Manual

Version 1.1

Architecture description

SMT351 block diagram

Figure 1 shows a block diagram of the SMT351 board. Refer to the following section
for additional information on the major blocks.
3 Power
Supply
LEDs
'FPGA configured'
On-board Oscillator
50 MHz
4 LEDs + 4 TTL IOs
2 x Sundance High-speed
Bus Connectors
2 x RSL Connectors
(8 RSL Interfaces)
configuration via
one of six
comports
6-pin JTAG

Figure 1: SMT351 board block diagram

J1 Top Primary TIM
Connector
2x ComPorts/SDLs
LED
Xilinx FPGA
VirtexII-Pro, FF896
XC2VP7,20,30
1.5V Core
2.5/3.3V I/O
FPGA
header
J2 Bottom Secondary TIM
Connector
4x ComPorts/SDLs
Page 8 of 24
40 I/O pins (D+@)
Clock + Feedback
40 I/O pins (D+@)
Clock + Feedback
40 I/O pins (D+@)
Clock + Feedback
40 I/O pins (D+@)
Clock + Feedback
SMT351 User Manual
External 5-Volt
Power Supply
converted to
2.5 Volts by a
DC-DC converter
128 (256) Mbytes DDR
RAM - MT46V16M16
128 (256) Mbytes DDR
RAM - MT46V16M16
128 (256) Mbytes DDR
RAM - MT46V16M16
128 (256) Mbytes DDR
RAM - MT46V16M16