Architecture Description - Sundance Spas SMT370v2 User Manual

Version 1.0 Page 8 of 44 SMT370v2 User Manual

Architecture Description.

The module consists of a Xilinx Virtex-II FPGA, two Analog Devices (14-bit monolithic
sampling Analog-to-Digital converters) AD6645 and one Analog Devices AD9777
(Dual TxDAC+ Digital-to-Analog converter).
The AD6645 is a 14-bit monolithic sampling analog-to-digital converter. The chip
provides CMOS-compatible digital outputs. It is the Analog Devices' fourth generation
of wideband ADCs. The AD6645 maintains outstanding AC performance up to input
frequencies of 200 MHz, which makes it suitable for multi-carrier 3G applications.
The AD6645 is able to sample from 30 up to 105 MHz. Nevertheless, it is possible to
reduce that rate by performing decimation on the data flow.
The AD9777 dual interpolating (2x/4x/8x) DAC consists of two data channels that can
be operated independently or coupled to form a complex modulator in an image
reject transmit architecture. This programmable converter has a resolution of 16 bits.
It features a Serial Port Interface (SPI) for programming. The chip features a
selectable 2x/4x/8x interpolation filter, an Fs/2, Fs/4 or Fs/8 digital quadrature
modulation with image rejection, a direct IF mode, a programmable channel gain and
offset control, a programmable internal clock divider, a straight binary to two's
complement data interface and a single port or dual data interface.
Parallel busses connect both ADCs and the DAC to the FPGA, which is responsible
for transferring samples from/to the converters. An on-board frequency synthesizer
generates differential encode lines (sampling clocks) to feed the converters; a
connector for external clocks is also available. Each input analogue signal to the
ADCs goes through an extra stage, which can be an opamp (DC coupling) or an RF
transformer (AC coupling). The option must be defined when ordering the SMT370.
When it comes to the DAC, its outputs can only be set as AC coupled (output RF
transformer). Both ADCs can be coupled together. i.e. they have the same sampling
clock or have two separate clocks, one external and one coming from the on-board
clock synthesizer.
The Xilinx FPGA Virtex-II is configured via a 6-pin JTAG header or from the on-board
Xilinx PROM (XC18V04) at startup. The default configuration mode is from a PROM,
which contains the standard modes of operation (as described in this document). An
on-board LED indicates that the FPGA is configured. Both devices, FPGA and
PROM are in the JTAG chain.
The SMT370 is also populated with some NtSRAM memory. It is 32-bit wide and to
store two 16-bit samples at the same address at up 160 MHz. Its size is 1
Megawords of 32-bits. The FPGA is implemented with an NtSRAM interface to
write/read to/from it. Memory accesses are made via the control register. A 'pattern
generator' function is available to store a pattern (or period or frame) into the
memory, read back continuously and send samples out to the DAC. This
configuration allows to board to work as a periodic generator in stand-alone mode.