Figure 10 - Clock Routing - Sundance Spas SMT370v2 User Manual

Version 1.0
F = (M/N) MHz -
Synthesized
the following values: 1, 1.5, 2, 3, 4, 6, 8 or 12 (for respectively "000"... "111"
encoding). See ICS8430-01
The following diagram shows how clock signals can be routed on the board.
Xilinx
FPGA
Virtex-II, FG456
XC2V1000-6
324 I/O Pins
1.5V Core
3.3V I/O
Page 32 of 44
With 500 < M < 250 (binary encoding) and N can take one of
datasheet for more information performance, jitter, etc.
30 I/O pins; 28-bit data; ctl
Clock feedbacks
A and B
Clock feedback
44 I/O pins; 16-bit data; ctl

Figure 10 - Clock Routing.

#1
AC or DC
AC or DC
coupling
coupling
2xAD6645 ADCs
14-bit @ 105MSPS
52-pin LQFP
ADC A
0 0
1 1
Bit26 Bit27
Bit24 Bit25
0
0
1 1
1x AD9777 DAC
16-bit @ 400MSPS
80-pin TQFP
RF
transformer
transformer
#3
SMT370v2 User Manual
#2
ADC B
Clock synthe-
sizer ADCs
Clk
1
opamp
opamp
Clk
2
Clock synthe-
sizer DAC
RF
#4