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SMT370v2 User Manual
reading it back continuously and sending data out to the DAC. This generator is
controlled via bits in the control registers. It can be loaded, started and stopped by
setting bits. For more details, see further in the documentation, the part dealing with
control registers.
Clock management.
The SMT370 has two identical on-board low-jitter clock synthesizers, one for the
ADCs and one for the DAC. Both have a Serial Port Interface. The FPGA is
responsible for setting them to the correct values loaded into a control register. A
wide range of frequencies can be set this way. They are low-jitter devices.
Clock multiplexers are also available on the board to route the appropriate clock
signal (from external or on-board source) to the converters. It is usual to have both
ADCs fed with the same sampling clock but it is possible to have an ADC receiving
the external clock and the second one receiving the on-board clock. In this particular
case, two 16-bit interfaces are necessary to transfer samples to an external TIM. The
DAC is fed either with an on-board/DAC or external clock coming from connector
J14. The clock selection is made via the control register.
TTL I/Os.
Four TTL I/Os (J6 – see Figure 9 - Connector Location.) are connected directly to the
FPGA. They support LVTTL signals. It is recommended to make sure the lines
connected to these pins are LVTTL compatible in order not to damage the FPGA
pads, as lines are not clamped.
External triggering.
Two external trigger connectors (J15 and J16 – see Figure 9 - Connector Location.)
are available on the board to trigger converters from an external source. The
selection is made via a control register, where channel selection can also be set.
Triggering consists in enabling or stopping the converters (ADCs and/or DAC). This
is available and accurate as long as the triggering signals are synchronised on the
sampling clock. Triggering signals can be set as active high or low in via the control
register.
Each trigger input is clamped to 3.3 and Ground to avoid damaging the FPGA I/Os.
This is achieved by using single diodes (BAV99). These diodes can support as
maximum, 200mA of forward current and 70 Volts of reverse voltage. It is to the
customer to consider this when building a system using an SMT370.
ADCs and DAC.
The SMT370 is populated with two
AD6645s
and one AD9777. For mode details
about these converters (inner characteristics), please refer to the manufacturer
(Analog Devices) datasheets.
Data and control lines of the converters are all connected to the.
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