Shb; Memory - Sundance Spas SMT370v2 User Manual

Version 1.0 Page 10 of 44 SMT370v2 User Manual
SMT365 for instance. Please report to the part dealing with CommPorts in this
document for more details.

SHB.

The SMT370 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled
SHBA (J3) and SHBB (J4) – see Figure 9 - Connector Location..
SHBA is set as transmitter only to transfer data coming from the Analogue-to-Digital
Converters to an external SHB module, for instance SMT365, SMT365E or SMT374.
SHBB is set as a receiver only and is dedicated to receive data for the Digital-to-
Analogue converter. Transfers at up to 100 MHz are supported on these two SHB
connectors.
SHBA – ADCs.
The FPGA routes the data lines coming from the ADCs to SHBA. Data lines go
through 7 latch stages inside the FPGA, which means that it takes 7 sampling clock
cycles for a sample to go from the ADC to SHBA. The board offers to possibility to
output data in either two's complement or binary format. The option of outputting a
counter is also available for system testing purpose.
As the SMT370 is populated with two ADCS, two data stream are theoretically
available on SHBA. Each of them can be synchronised to either an external sampling
clock or an on-board clock. In the FPGA, each data stream goes through a
Decimator, which value (0 to 31) can be set in a control register. Both decimators are
independent. If both decimators are set with the same values and if the sampling
clocks (for Channel A and Channel B) are the same, i.e. both ADCs are using either
the external or the on-board clock, both data streams are synchronised with each
other and therefore the two 16-bit data streams can be considered as a single 32-bit
data stream.
It is possible to control (start/stop) the data flow by the way of an external trigger, for
which the active level (high or low) can be set in a control register. It is recommended
to have external trigger signal synchronised to the sampling clock. This external
trigger also goes thought 7 latch stages.
SHBB – DAC.
Data received from SHBB are samples routed to the DAC. Data from both SHBB
channels are first stored into a FIFO. As they are not necessarily synchronised, the
two FIFOs are read out at the same time as soon as there is a least one data in each
FIFO. This is what happens when using two independent 16-bit interfaces. To avoid
synchronisation problems, SHBB can be configured as a single 32-bit interface.

Memory.

The SMT370 is populated with 32Mbits of ZBTRAM (32 bits x 1Meg). It is connected
to the FPGA, which controls read and write operations. The default FPGA bit stream
implements a pattern generator which consists in storing a pattern into the memory,