Clock Structure; Figure 4: Fpga's Clock Domains; Table 4: Fpga's Clock Domains Description - Sundance Spas SMT351 User Manual

Version 1.1

Clock structure

This section describes the various clock domains in the FPGA.
The figure below shows the four clock domains of the SMT351 design and their
interrelation.
Control Com
Registers
words port
SHB
A
Input clock
domain

Figure 4: FPGA's clock domains

Table 4: FPGA's clock domains description

Clock domain Colour
ComPort
Data input
Data output
DDR SDRAM
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Memory bank 0
Input DDR SDRAM
buffer
clock domain
Memory bank 1
Frequency
50 MHz
< 100 MHz
100 MHz
100 MHz
SMT351 User Manual
Output
Mux
buffer
Description
Comport and registers clock
SHB A clock.
SHB B clock.
DDR SDRAM clock.
SHB
B
Output clock
domain