Module States; Local Reset; Executing State Transitions; Power Domain State Transitions - Texas Instruments TMS320C6457 User Manual

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2.2.2

Module States

A module can be in one of two states: Enable or SwRstDisable. As shown in
correspond to combinations of module reset asserted or de-asserted and module clock on or off. Note that
module reset is defined to completely reset a given module, such that all hardware is put back into its
default state. For more information on module reset, see Curie Chip Architecture (XXXX-SYS-FS-001)
Revision XXXX.
Module State
SwRstDisable
The module states are defined as follows:
• Enable: A module in the Enable state has its module reset de-asserted and its clock on. This is the
normal run-time state for a given module.
• SwRstDisable: A module in the SwResetDisable state has its module reset asserted and its clock
OFF. This state is not expected to be initiated by software.
2.2.3

Local Reset

In addition to module reset described in the previous section, the C64x+ CPU can be reset using a special
local reset. When local reset is asserted, the internal memories (L1P, L1D, and L2) for the core are still
accessible. The local reset only resets the corresponding C64x+ core, not the rest of the chip. Local reset
is intended to be used by the watchdog timers to reset the C64x+ core in the event of an error. The
procedures for asserting and de-asserting local reset are as follows (Y denotes the module domain
number):
• Set MDCTL[Y].LRSTZ to 0x0 to assert local reset.
• Set MDCTL[Y].LRSTZ to 0x1 to de-assert local reset. The 64x+ core immediately executes program
instructions after reset is de-asserted. Note that the boot sequence does not re-occur unless there is a
chip-level reset. Execution of code previously in L2 begins execution.
2.3

Executing State Transitions

This section describes how to execute state transitions for power domains and modules. Examples show
how to enable only power domains, only modules, or a combination. Although you have complete control
of the sequencing, for TI recommendations, see
2.3.1

Power Domain State Transitions

This section describes the basic procedure for transitioning the state of a power domain which, in the case
of the C6457 device is limited to the memories located in a particular domain. The majority of the modules
on the chip are always in the ON state. The PSC handles all required internal operations to wake
memories for the controlled power domains.
Note: As mentioned previously, in the C6457 device there are multiple power domains. The
AlwaysOn power domain is always in the ON state when the chip is powered-on, and
therefore it is not possible to transition this domain to the OFF state. Conversely, the other
domains are in the OFF states when the chip is powered-on. Transitions from ON to OFF are
never allowed.
The procedure for power domain state transitions follows (X denotes the power domain number, Y
denotes the module domain number):
• Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finish
before initiating a new transition.
SPRUGL4 – March 2009
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Table 3. Module States
Enable
Module Reset
De-asserted
Asserted
Section 2.3.4.
TMS320C6457 DSP Power/Sleep Controller (PSC)
Power/Sleep Controller
Table 3, these two states
Module Clock
ON
OFF
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