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TMS320C645X
Texas Instruments TMS320C645X Manuals
Manuals and User Guides for Texas Instruments TMS320C645X. We have
3
Texas Instruments TMS320C645X manuals available for free PDF download: User Manual
Texas Instruments TMS320C645X User Manual (218 pages)
Texas Instruments Musical Instrument Amplifier User Manual
Brand:
Texas Instruments
| Category:
Musical Instrument Amplifier
| Size: 3 MB
Table of Contents
Table of Contents
3
Error, Reset, and Special Event Interrupt Condition Routing Register
3
Preface
13
Read this First
13
1 Overview
14
General Rapidio System
14
Rapidio Architectural Hierarchy
15
Rapidio Interconnect Architecture
16
Rapidio Feature Support in SRIO
17
Serial Rapidio Device to Device Interface Diagrams
17
Standards
18
External Devices Requirements
18
Rapidio Documents and Links
18
2 SRIO Functional Description
19
Overview
19
SRIO Peripheral Block Diagram
20
Operation Sequence
21
1X/4X Rapidio Packet Data Stream (Streaming-Write Class)
22
Serial Rapidio Control Symbol Format
22
Packet Type
23
SRIO Pins
24
Functional Operation
24
Pin Description
24
SRIO Conceptual Block Diagram
25
Bits of Serdes_Cfgn_Cntl Register (0X120 - 0X12C)
26
Line Rate Versus PLL Output Clock Frequency
27
RATE Bit Effects
27
Frequency Range Versus MPY
28
Bits of Serdes_Cfgrxn_Cntl Registers
28
EQ Bits
30
Bits of Serdes_Cfgtxn_Cntl Registers
30
SWING Bits
31
DE Bits
31
Load/Store Data Transfer Diagram
32
Load/Store Registers for Rapidio (Address Offset: LSU1 0X400-0X418, LSU2 0X420-0X438, LSU3 0X440-0X458, LSU4 0X460-0X478)
33
Control/Command Register Field Mapping
33
Status Fields
34
LSU Registers Timing
35
Example Burst NWRITE_R
36
Load/Store Module Data Flow
37
CPPI RX Scheme for Rapidio
41
Message Request Packet
41
Queue Mapping Table (Address Offset: 0X0800 - 0X08Fc)
42
Queue Mapping Register Rxu_Map_Ln
43
Queue Mapping Register Rxu_Map_Hn
43
RX DMA State Head Descriptor Pointer (HDP) (Address Offset 0X600-0X63C)
43
RX DMA State Completion Pointer (CP) (Address Offset 0X600-0X63C)
43
RX Buffer Descriptor Fields
44
RX Buffer Descriptor Field Descriptions
45
SRIO Functional Description
45
RX CPPI Mode Explanation
47
CPPI Boundary Diagram
48
TX Buffer Descriptor Fields
49
TX DMA State Head Descriptor Pointer (HDP) (Address Offset 0X500 - 0X53C)
49
TX DMA State Completion Pointer (CP) (Address Offset 0X580 - 0X5Bc)
49
TX Buffer Descriptor Field Definitions
49
Weighted Round Robin Programming Registers (Address Offset 0X7E0 - 0X7Ec)
52
Queue Mapping
56
RX Buffer Descriptor
56
RX Buffer Descriptor
57
Maintenance
58
TX Buffer Descriptor
58
Doorbell Operation
59
Flow Control Table Entry Registers (Address Offset 0X0900 - 0X093C)
61
Transmit Source Flow Control Masks
62
Configuration Bus Example
63
DMA Example
64
GBL_EN (Address 0X0030)
65
GBL_EN_STAT (Address 0X0034)
65
BLK0_EN (Address 0X0038)
65
BLK0_EN_STAT (Address 0X003C)
66
BLK1_EN (Address 0X0040)
66
BLK1_EN_STAT (Address 0X0044)
66
BLK8_EN (Address 0X0078)
66
BLK8_EN_STAT (Address 0X007C)
66
Enable and Enable Status Bit Field Descriptions
66
Emulation Control (Peripheral Control Register PCR 0X0004)
68
Emulation Control Signals
69
Bootload Operation
72
3 Logical/Transport Error Handling and Logging
73
Detectable Errors
73
4 Interrupt Conditions
74
CPU Interrupts
74
General Description
74
Rapidio DOORBELL Packet for Interrupt Use
74
Interrupt Condition Control Registers
75
DOORBELL0 Interrupt Registers for Direct I/O Transfers
76
DOORBELL1 Interrupt Registers for Direct I/O Transfers
76
Interrupt Source Configuration Options
76
DOORBELL2 Interrupt Registers for Direct I/O Transfers
77
DOORBELL3 Interrupt Registers for Direct I/O Transfers
77
RX_CPPI Interrupts Using Messaging Mode Data Transfers
78
TX _CPPI Interrupts Using Messaging Mode Data Transfers
78
LSU Load/Store Module Interrupts
79
ERR_RST_EVNT Error, Reset, and Special Event Interrupt
80
Doorbell 0 Interrupt Condition Routing Registers
81
Interrupt Condition Routing Options
81
Load/Store Module Interrupt Condition Routing Registers
82
Interrupt Status Decode Registers
83
Error, Reset, and Special Event Interrupt Condition Routing Registers
83
Example Diagram of Interrupt Status Decode Register Mapping
84
Sharing of ISDR Bits
84
Interrupt Generation
85
Interrupt Pacing
85
Intdstn_Decode Interrupt Status Decode Register
85
Interrupt Handling
86
Intdstn_Rate_Cntl Interrupt Rate Control Register
86
5 SRIO Registers
88
Introduction
88
Serial Rapid IO (SRIO) Registers
88
Peripheral Identification Register (PID)
99
Peripheral ID Register (PID) Field Descriptions
99
Peripheral Control Register (PCR)
100
Peripheral Control Register (PCR) Field Descriptions
100
Peripheral Settings Control Register (PER_SET_CNTL)
101
Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions
101
Peripheral Global Enable Register (GBL_EN)
104
Peripheral Global Enable Register (GBL_EN) Field Descriptions
104
Peripheral Global Enable Status Register (GBL_EN_STAT)
105
Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions
105
Block N Enable Register (Blkn_En)
106
Block N Enable Register (Blkn_En) Field Descriptions
106
Block N Enable Status Register (Blkn_En_Stat)
107
Block N Enable Status Register (Blkn_En_Stat) Field Descriptions
107
Rapidio DEVICEID1 Register (DEVICEID_REG1)
108
Rapidio DEVICEID1 Register (DEVICEID_REG1) Field Descriptions
108
Rapidio DEVICEID2 Register (DEVICEID_REG2)
109
Rapidio DEVICEID2 Register (DEVICEID_REG2) Field Descriptions
109
Packet Forwarding Register N for 16B Deviceids (Pf_16B_Cntln)
110
Packet Forwarding Register N for 16B Deviceids (Pf_16B_Cntln) Field Descriptions
110
Packet Forwarding Register N for 8B Deviceids (Pf_8B_Cntln)
111
Packet Forwarding Register N for 8B Deviceids (Pf_8B_Cntln) Field Descriptions
111
SERDES Receive Channel Configuration Registers N (Serdes_Cfgrxn_Cntl)
112
EQ Bits
113
SRIO Registers
113
SERDES Transmit Channel Configuration Registers N (Serdes_Cfgtxn_Cntl)
114
SWING Bits
115
DE Bits
115
SERDES Macro Configuration Register N (Serdes_Cfgn_Cntl)
116
SERDES Macros CFG (0-3) Registers (Serdes_Cfgn_Cntl) Field Descriptions
116
Doorbelln Interrupt Status Register (Doorbelln_Icsr)
117
Doorbelln Interrupt Status Register (Doorbelln_Icsr) Field Descriptions
117
Doorbelln Interrupt Clear Register (Doorbelln_Iccr)
118
Doorbelln Interrupt Clear Register (Doorbelln_Iccr) Field Descriptions
118
RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
119
RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descriptions
119
RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)
120
RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descriptions
120
TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
121
TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions
121
TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
122
TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions
122
LSU Status Interrupt Register (LSU_ICSR)
123
LSU Status Interrupt Register (LSU_ICSR) Field Descriptions
123
LSU Clear Interrupt Register (LSU
124
LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions
124
Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR)
125
Descriptions
125
Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR)
126
Descriptions
126
Doorbelln Interrupt Condition Routing Register (Doorbelln_Icrr)
127
Doorbelln Interrupt Condition Routing Register 2 (Doorbelln_Icrr2)
128
RX CPPI Interrupt Condition Routing Register (RX_CPPI
129
RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Field Descriptions
129
RX CPPI Interrupt Condition Routing Register (RX_CPPI
130
RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Field Descriptions
130
TX CPPI Interrupt Condition Routing Register (TX_CPPI
131
TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Field Descriptions
131
TX CPPI Interrupt Condition Routing Register (TX_CPPI
132
TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Field Descriptions
132
LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0)
133
LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Field Descriptions
133
LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1)
134
LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Field Descriptions
134
LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2)
135
LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Field Descriptions
135
LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3)
136
LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Field Descriptions
136
Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR)
137
Error, Reset, and Special Event Interrupt Condition Routing Register
137
Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) Field
137
(Err_Rst_Evnt_Icrr2)
138
Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2)
138
(Err_Rst_Evnt_Icrr3)
139
Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3)
139
Intdstn Interrupt Status Decode Registers (Intdstn_Decode)
140
Intdstn Interrupt Status Decode Registers (Intdstn_Decode) Field Descriptions
140
Intdstn Interrupt Rate Control Registers (Intdstn_Rate_Cntl)
141
Intdstn Interrupt Rate Control Registers (Intdstn_Rate_Cntl) Field Descriptions
141
Lsun Control Register 0 (Lsun_Reg0)
142
Lsun Control Register 0 (Lsun_Reg0) Field Descriptions
142
Lsun Control Register 1 (Lsun_Reg1)
143
Lsun Control Register 1 (Lsun_Reg1) Field Descriptions
143
Lsun Control Register 2 (Lsun_Reg2)
144
Lsun Control Register 2 (Lsun_Reg2) Field Descriptions
144
Lsun Control Register 3 (Lsun_Reg3)
145
Lsun Control Register 3 (Lsun_Reg3) Field Descriptions
145
Lsun Control Register 4 (Lsun_Reg4)
146
Lsun Control Register 4 (Lsun_Reg4) Field Descriptions
146
Lsun Control Register 5 (Lsun_Reg5)
147
Lsun Control Register 5 (Lsun_Reg5) Field Descriptions
147
Lsun Control Register 6 (Lsun_Reg6)
148
Lsun Control Register 6 (Lsun_Reg6) Field Descriptions
148
LSU Congestion Control Flow Mask N (LSU_FLOW_MASKS N)
149
LSU Congestion Control Flow Mask N (LSU_FLOW_MASKS N) Field Descriptions
149
Queue Transmit DMA Head Descriptor Pointer Registers (Queuen_Txdma_Hdp)
150
Queue Transmit DMA Completion Pointer Registers (Queuen_Txdma_Cp)
151
Queue Receive DMA Head Descriptor Pointer Registers (Queuen_Rxdma_Hdp)
152
Queue Receive DMA Completion Pointer Registers (Queuen_Rxdma_Cp)
153
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)
154
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions
154
Transmit CPPI Supported Flow Mask Registers N (Tx_Cppi_Flow_Masksn)
155
Transmit CPPI Supported Flow Mask Registers N (Tx_Cppi_Flow_Masksn) Field Descriptions
156
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)
157
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions
157
Receive CPPI Control Register (RX_CPPI_CNTL)
158
Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions
158
Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0)
159
Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1)
160
Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2)
161
Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3)
162
Mailbox-To-Queue Mapping Register Ln (Rxu_Map_Ln)
163
Mailbox-To-Queue Mapping Register Ln (Rxu_Map_Ln) Field Descriptions
163
Mailbox-To-Queue Mapping Register Hn (Rxu_Map_Hn)
164
Mailbox-To-Queue Mapping Register Hn (Rxu_Map_Hn) Field Descriptions
164
Flow Control Table Entry Registers (Flow_Cntln)
165
Flow Control Table Entry Registers (Flow_Cntln) Field Descriptions
165
Device Identity CAR (DEV_ID)
166
Device Identity CAR (DEV_ID) Field Descriptions
166
Device Information CAR (DEV_INFO)
167
Device Information CAR (DEV_INFO) Field Descriptions
167
Assembly Identity CAR (ASBLY_ID)
168
Assembly Identity CAR (ASBLY_ID) Field Descriptions
168
Assembly Information CAR (ASBLY_INFO)
169
Assembly Information CAR (ASBLY_INFO) Field Descriptions
169
Processing Element Features CAR (PE_FEAT)
170
Processing Element Features CAR (PE_FEAT) Field Descriptions
170
Source Operations CAR (SRC_OP)
171
Source Operations CAR (SRC_OP) Field Descriptions
171
Destination Operations CAR (DEST_OP)
172
Destination Operations CAR (DEST_OP) Field Descriptions
172
Processing Element Logical Layer Control CSR (PE_LL_CTL)
173
Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
173
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions
174
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions
175
Base Device ID CSR (BASE_ID) Field Descriptions
176
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions
177
Component Tag CSR (COMP_TAG) Field Descriptions
178
X/4X Lp_Serial Port Maintenance Block Header Register (SP_MB_HEAD)
179
Descriptions
179
Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
180
Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions
181
Port General Control CSR (SP_GEN_CTL) Field Descriptions
182
Port Link Maintenance Request CSR N (Spn_Lm_Req) Field Descriptions
183
Port Link Maintenance Response CSR N (Spn_Lm_Resp) Field Descriptions
184
Port Local Ackid Status CSR N (Spn_Ackid_Stat) Field Descriptions
185
Port Error and Status CSR N (Spn_Err_Stat) Field Descriptions
186
Port Control CSR N (Spn_Ctl) Field Descriptions
188
Error Reporting Block Header (ERR_RPT_BH) Field Descriptions
190
Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
191
Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions
192
Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions
193
Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions
194
Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions
195
Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions
196
Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions
197
Port Error Detect CSR N (Spn_Err_Det) Field Descriptions
198
Port Error Rate Enable CSR N (Spn_Rate_En) Field Descriptions
199
Port N Attributes Error Capture CSR 0 (Spn_Err_Attr_Capt_Dbg0)
200
Port N Packet/Control Symbol Error Capture CSR 1 (Spn_Err_Capt_Dbg1)
201
Port N Packet/Control Symbol Error Capture CSR 2 (Spn_Err_Capt_Dbg2)
202
Port N Packet/Control Symbol Error Capture CSR 3 (Spn_Err_Capt_Dbg3)
203
Port N Packet/Control Symbol Error Capture CSR 4 (Spn_Err_Capt_Dbg4)
204
Port Error Rate CSR N (Spn_Err_Rate) Field Descriptions
205
Port Error Rate Threshold CSR N (Spn_Err_Thresh) Field Descriptions
206
Port IP Discovery Timer in 4X Mode (SP_IP_DISCOVERY_TIMER) Field Descriptions
207
Port IP Mode CSR (SP_IP_MODE) Field Descriptions
208
Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions
210
Port-Write-In Capture CSR N (Sp_Ip_Pw_In_Captn) Field Descriptions
211
Port Reset Option CSR N (Spn_Rst_Opt) Field Descriptions
212
Port Control Independent Register N (Spn_Ctl_Indep) Field Descriptions
213
Port Silence Timer N (Spn_Silence_Timer) Field Descriptions
215
Port Multicast-Event Control Symbol Request Register N (Spn_Mult_Evnt_Cs)
216
Port Control Symbol Transmit N (Spn_Cs_Tx) Field Descriptions
217
Important Notice
218
Advertisement
Texas Instruments TMS320C645X User Manual (148 pages)
DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO)
Brand:
Texas Instruments
| Category:
IP Access Controllers
| Size: 1 MB
Table of Contents
Table of Contents
3
Preface
10
Read this First
10
Introduction
11
Purpose of the Peripheral
11
Features
11
Functional Block Diagram
12
EMAC and MDIO Block Diagram
12
Industry Standard(S) Compliance Statement
13
EMAC Functional Architecture
14
Clock Control
14
Memory Map
15
System Level Connections
16
Ethernet Configuration with MII Interface
16
Interface Selection Pins
16
EMAC and MDIO Signals for MII Interface
17
Ethernet Configuration with RMII Interface
18
EMAC and MDIO Signals for RMII Interface
19
Ethernet Configuration with GMII Interface
20
EMAC and MDIO Signals for GMII Interface
21
Ethernet Configuration with RGMII Interface
22
EMAC and MDIO Signals for RGMII Interface
23
Ethernet Protocol Overview
24
Ethernet Frame
24
Ethernet Frame Description
24
Programming Interface
26
Basic Descriptor Format
26
Basic Descriptors
26
Typical Descriptor Linked List
27
Transmit Descriptor Format
30
Receive Descriptor Format
33
EMAC Control Module
37
EMAC Control Module Block Diagram
37
Management Data Input/Output (MDIO) Module
38
MDIO Module Block Diagram
39
EMAC Module
43
EMAC Module Block Diagram
43
Media Independent Interfaces
46
2.10 Packet Receive Operation
50
Receive Frame Treatment Summary
53
Middle of Frame Overrun Treatment
54
2.11 Packet Transmit Operation
55
2.12 Receive and Transmit Latency
55
2.13 Transfer Node Priority
56
2.14 Reset Considerations
56
2.15 Initialization
57
2.16 Interrupt Support
60
2.17 Power Management
63
2.18 Emulation Considerations
63
Emulation Control
63
EMAC Control Module Registers
64
Introduction
64
EMAC Control Module Interrupt Control Register (EWCTL)
64
EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions
64
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)
65
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions
65
MDIO Registers
66
Introduction
66
Management Data Input/Output (MDIO) Registers
66
MDIO Version Register (VERSION)
67
MDIO Version Register (VERSION) Field Descriptions
67
MDIO Control Register (CONTROL)
68
MDIO Control Register (CONTROL) Field Descriptions
68
PHY Acknowledge Status Register (ALIVE)
69
PHY Acknowledge Status Register (ALIVE) Field Descriptions
69
PHY Link Status Register (LINK)
70
PHY Link Status Register (LINK) Field Descriptions
70
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
71
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
71
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
72
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
72
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
73
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
73
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
74
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
74
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
75
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
75
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
76
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
76
MDIO User Access Register 0 (USERACCESS0)
77
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
77
MDIO User PHY Select Register 0 (USERPHYSEL0)
78
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
78
MDIO User Access Register 1 (USERACCESS1)
79
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
79
MDIO User PHY Select Register 1 (USERPHYSEL1)
80
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
80
EMAC Port Registers
81
Introduction
81
Ethernet Media Access Controller (EMAC) Registers
81
Transmit Identification and Version Register (TXIDVER)
85
Transmit Identification and Version Register (TXIDVER) Field Descriptions
85
Transmit Control Register (TXCONTROL)
86
Transmit Control Register (TXCONTROL) Field Descriptions
86
Transmit Teardown Register (TXTEARDOWN)
87
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
87
Receive Identification and Version Register (RXIDVER)
88
Receive Identification and Version Register (RXIDVER) Field Descriptions
88
Receive Control Register (RXCONTROL)
89
Receive Control Register (RXCONTROL) Field Descriptions
89
Receive Teardown Register (RXTEARDOWN)
90
Receive Teardown Register (RXTEARDOWN) Field Descriptions
90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
91
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
91
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
92
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
92
Transmit Interrupt Mask Set Register (TXINTMASKSET)
93
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
93
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
94
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
94
MAC Input Vector Register (MACINVECTOR)
95
MAC Input Vector Register (MACINVECTOR) Field Descriptions
95
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
96
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
96
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
97
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
97
Receive Interrupt Mask Set Register (RXINTMASKSET)
98
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
98
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
99
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
99
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
100
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
100
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
101
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
101
MAC Interrupt Mask Set Register (MACINTMASKSET)
102
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
102
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
103
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
103
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
104
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions
104
Receive Unicast Enable Set Register (RXUNICASTSET)
106
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
106
Receive Unicast Clear Register (RXUNICASTCLEAR)
107
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
107
Receive Maximum Length Register (RXMAXLEN)
108
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
108
Receive Buffer Offset Register (RXBUFFEROFFSET)
109
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
109
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
110
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
110
Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)
111
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
111
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
111
Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)
112
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
112
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
112
MAC Control Register (MACCONTROL)
113
MAC Control Register (MACCONTROL) Field Descriptions
113
MAC Status Register (MACSTATUS)
115
MAC Status Register (MACSTATUS) Field Descriptions
115
Emulation Control Register (EMCONTROL)
117
Emulation Control Register (EMCONTROL) Field Descriptions
117
FIFO Control Register (FIFOCONTROL)
118
FIFO Control Register (FIFOCONTROL) Field Descriptions
118
MAC Configuration Register (MACCONFIG)
119
MAC Configuration Register (MACCONFIG) Field Descriptions
119
Soft Reset Register (SOFTRESET)
120
Soft Reset Register (SOFTRESET) Field Descriptions
120
MAC Source Address Low Bytes Register (MACSRCADDRLO)
121
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
121
MAC Source Address High Bytes Register (MACSRCADDRHI)
122
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
122
MAC Hash Address Register 1 (MACHASH1)
123
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
123
MAC Hash Address Register 2 (MACHASH2)
124
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
124
Back off Test Register (BOFFTEST)
125
Back off Random Number Generator Test Register (BOFFTEST)
125
Back off Test Register (BOFFTEST) Field Descriptions
125
Transmit Pacing Algorithm Test Register (TPACETEST)
126
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
126
Receive Pause Timer Register (RXPAUSE)
127
Receive Pause Timer Register (RXPAUSE) Field Descriptions
127
Transmit Pause Timer Register (TXPAUSE)
128
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
128
MAC Address Low Bytes Register (MACADDRLO)
129
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
129
MAC Address High Bytes Register (MACADDRHI)
130
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
130
MAC Index Register (MACINDEX)
131
MAC Index Register (MACINDEX) Field Descriptions
131
Transmit Channel 0-7 DMA Head Descriptor Pointer Register (Txnhdp)
132
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
132
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
132
Receive Channel 0-7 DMA Head Descriptor Pointer Register (Rxnhdp)
133
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
133
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
133
Transmit Channel 0-7 Completion Pointer Register (Txncp)
134
Transmit Channel N Completion Pointer Register (Txncp)
134
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
134
Receive Channel 0-7 Completion Pointer Register (Rxncp)
135
Receive Channel N Completion Pointer Register (Rxncp)
135
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
135
5.50 Network Statistics Registers
136
Statistics Register
136
Statistics Register Field Descriptions
136
Appendix A Glossary
145
Physical Layer Definitions
146
Appendix B Revision History
147
Document Revision History
147
Texas Instruments TMS320C645X User Manual (27 pages)
TMS320C645x General-Purpose Input/Output SPRU724 User's Guide
Brand:
Texas Instruments
| Category:
Network Card
| Size: 0 MB
Table of Contents
About this Manual
3
Notational Conventions
3
Read this First
3
Related Documentation from Texas Instruments
3
Table of Contents
5
Overview
9
Tms320C645X DSP Block Diagram
10
GPIO Peripheral Block Diagram
11
GPIO Function
12
Interrupt and Event Generation
13
GPIO Interrupt and EDMA Event Configuration Options
13
Emulation Halt Operation
14
Registers
15
GPIO Registers
15
Interrupt Per-Bank Enable Register (BINTEN)
16
Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions
16
Direction Register (DIR)
17
Direction Register (DIR) Field Descriptions
17
Output Data Register (OUT_DATA)
18
Output Data Register (OUT_DATA) Field Descriptions
18
Set Data Register (SET_DATA)
19
Set Data Register (SET_DATA) Field Descriptions
19
Clear Data Register (CLR_DATA)
20
Clear Data Register (CLR_DATA) Field Descriptions
20
Input Data Register (IN_DATA)
21
Input Data Register (IN_DATA) Field Descriptions
21
Set Rising Edge Interrupt Register (SET_RIS_TRIG)
22
Set Rising Edge Interrupt Register (SET_RIS_TRIG) Field Descriptions
22
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG)
23
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) Field Descriptions
23
Set Falling Edge Interrupt Register (SET_FAL_TRIG)
24
Set Falling Edge Interrupt Register (SET_FAL_TRIG) Field Descriptions
24
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG)
25
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) Field Descriptions
25
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