Texas Instruments TMS320C6457 User Manual
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Texas Instruments TMS320C6457 User Manual

Texas Instruments TMS320C6457 User Manual

Dsp host port interface (hpi)
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TMS320C6457 DSP
Host Port Interface (HPI)
User's Guide
Literature Number: SPRUGK7A
March 2009 – Revised July 2010

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Summary of Contents for Texas Instruments TMS320C6457

  • Page 1 TMS320C6457 DSP Host Port Interface (HPI) User's Guide Literature Number: SPRUGK7A March 2009 – Revised July 2010...
  • Page 2 SPRUGK7A – March 2009 – Revised July 2010 Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    Power and Emulation Management Register (PWREMU_MGMT) Host Port Interface Control Register (HPIC) Host Port Interface Address Registers (HPIAW and HPIAR) Data Register (HPID) Appendix A Revision History SPRUGK7A – March 2009 – Revised July 2010 Copyright © 2009–2010, Texas Instruments Incorporated Table of Contents...
  • Page 4 Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions Data Register (HPID) (Host access permissions, CPU cannot access HPID) List of Figures List of Figures Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...
  • Page 5 Host Port Interface Control Register (HPIC) Field Descriptions Host Port Interface Address Registers (HPIAW or HPIAR) Field Descriptions Data Register (HPID) Field Descriptions TMS320C6457 HPI Revision History SPRUGK7A – March 2009 – Revised July 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated List of Tables...

  • Page 6: About This Manual

    About This Manual This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access the internal or external memory of the DSP using a 16-bit (HPI16) or 32-bit (HPI32) interface.

  • Page 7: Introduction To The Hpi

    This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access DSP resources (including internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface.

  • Page 8: Summary Of The Hpi Registers

    HPI registers. Host Port Interface (HPI) Section Section 8 describes the effects of the HCNTL[1:0] signals. The HR/W signal indicates Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com for detailed descriptions of all these Table 1 shows the offset SPRUGK7A – March 2009 – Revised July 2010...

  • Page 9: Summary Of The Hpi Signals

    During an HPID write access, data is latched into the HPID register on the rising edge of HDS. During read operations, these pins act as output-enable pins of the host data bus. Copyright © 2009–2010, Texas Instruments Incorporated Introduction to the HPI CPU Access Read/Write...
  • Page 10 1 to the HINT bit. This pin is active-low and inverted from the HINT bit value in HPIC. Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Section 3.3). The four...

  • Page 11: Using The Address Registers

    In an autoincrement write cycle, HPIAW is incremented after it has been used for the write operation. SPRUGK7A – March 2009 – Revised July 2010 CAUTION Copyright © 2009–2010, Texas Instruments Incorporated Using the Address Registers Host Port Interface (HPI)

  • Page 12: Hpi Operation

    32-Bit Multiplexed Mode HCNTL[1:0] No connect HHWIL HR/W Logic high HDS1 HDS2 HD[31:0] Ready HRDY HINT Section 3.3. Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 4 Figure 2 Figure 4, the HAS signal SPRUGK7A – March 2009 – Revised July 2010...

  • Page 13: Example Of Host-Dsp Signal Connections When The Has Signal Is Tied High In The 32-Bit Multiplexed Mode

    Logic high HDS1 HDS2 HD[31:0] Ready HRDY HINT Section 3.3. in the 16-Bit Multiplexed Mode HCNTL[1:0] HHWIL HR/W Logic HDS1 high HDS2 HD[31:16] connect HD[15:0] HRDY HINT Section 3.3. Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation Host Port Interface (HPI)

  • Page 14: Hpi Configuration And Data Flow

    HDS2 No connect HD[31:16] HD[15:0] HRDY HINT Section 3.3. 3.6). After the control information is latched, the HPI initiates an access Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Section 3.3) or the SPRUGK7A – March 2009 – Revised July 2010...

  • Page 15: Hds2, Hds1, And Hcs: Data Strobing And Chip Selection

    Connect the strobe pin to HDS1 or HDS2, and connect the other pin to logic level 1. Connect the strobe pin to HDS1 or HDS2, and connect the other pin to logic level 0. Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation...

  • Page 16: Hcntl[1:0] And Hr/W: Indicating The Cycle Type

    HPID write cycle with autoincrementing HPID read cycle with autoincrementing HPIA write cycle HPIA read cycle HPID write cycle without autoincrementing HPID read cycle without autoincrementing Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...

  • Page 17: Hhwil: Identifying The First And Second Halfwords In 16-Bit Multiplexed Mode

    HCNTL [1:0], HR/W, and HHWIL. SPRUGK7A – March 2009 – Revised July 2010 Section 3.9 Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation Section 3.6 includes an example timing...

  • Page 18: Bit Multiplexed Mode Host Read Cycle Using Has

    FIFO, transitions on HRDY may or may not occur. For more information, see Section 3.9. Host Port Interface (HPI) Data 1 Host latches HPI latches data control information Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Data 2 Host latches data SPRUGK7A – March 2009 – Revised July 2010...

  • Page 19: Bit Multiplexed Mode Host Write Cycle Using Has

    FIFO, transitions on HRDY may or may not occur. For more information, see Section 3.9. SPRUGK7A – March 2009 – Revised July 2010 Data 1 HPI latches control information HPI latches data Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation Data 2 HPI latches data Host Port Interface (HPI)

  • Page 20: Performing A Multiplexed Access Without Has

    Section 3.9. Host Port Interface (HPI) Figure 9 Data 1 Host latches data control information Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 10 show typical HPI Data 2 HPI latches Host latches data SPRUGK7A – March 2009 – Revised July 2010...

  • Page 21: Bit Multiplexed Mode Host Write Cycle With Has Tied High

    FIFO, transitions on HRDY may or may not occur. For more information, see Section 3.9. SPRUGK7A – March 2009 – Revised July 2010 Data 1 HPI latches control information HPI latches data Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation Data 2 HPI latches data Host Port Interface (HPI)

  • Page 22: Single-Halfword Hpic Cycle In The 16-Bit Multiplexed Mode

    HPI. The FIFOs are explained in Section Host Port Interface (HPI) 3.5). Although the example in Figure 11 Valid Data 1 Valid Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com has the HAS signal tied high, this SPRUGK7A – March 2009 – Revised July 2010...

  • Page 23: Hrdy Behavior During An Hpic Or Hpia Read Cycle In The 16-Bit Multiplexed Mode

    SPRUGK7A – March 2009 – Revised July 2010 00 or 10 1st halfword HPIA write 2nd halfword 2nd halfword 1st halfword Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation 2nd halfword HPID read 1st halfword 2nd halfword HPID+ reads 2nd halfword...

  • Page 24: Hrdy Behavior During An Hpic Write Cycle In The 16-Bit Multiplexed Mode

    (Case 1: No Autoincrementing) 2nd halfword 1st halfword 2nd halfword 1st halfword Figure 17. However, in Figure Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com 2nd halfword HPID write 2nd halfword HPID+ writes 2nd halfword 1st halfword 18, the write FIFO is not empty...

  • Page 25: Hrdy Behavior During A Data Write Operation In The 16-Bit Multiplexed Mode(Case 3: Autoincrementing Selected, Fifo Not Empty Before Write)

    HPIA (HCNTL[1:0] = 10b) write access followed by an HPID (HCNTL[1:0] = 11b) read access for 32-bit multiplexed HPI operation. SPRUGK7A – March 2009 – Revised July 2010 2nd halfword 1st halfword 00 or 10 Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation HPID+ writes 2nd halfword 1st halfword Host Port Interface (HPI)

  • Page 26: Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode (Case 1: Hpia Write Cycle Followed By Nonautoincrement Hpid Read Cycle)

    HPIC (HCNTL[1:0] = 00b) write access for 32-bit multiplexed HPI operation. Note that an HPIC write access does not cause HRDY to become active. Host Port Interface (HPI) HPIA Write HPIA Write Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com HPID Read HPID+ Reads SPRUGK7A – March 2009 – Revised July 2010...

  • Page 27: Hrdy Behavior During An Hpic Write Cycle In The 32-Bit Multiplexed Mode

    (HCNTL[1:0] = 01b) write accesses when the write FIFO is empty. Note that HRDY is active during the HPIA access but not active during any of the HPID accesses. SPRUGK7A – March 2009 – Revised July 2010 (Case 1: No Autoincrementing) HPIA Write Copyright © 2009–2010, Texas Instruments Incorporated HPI Operation HPID Write Host Port Interface (HPI)

  • Page 28: Hrdy Behavior During A Data Write Operation In The 32-Bit Multiplexed Mode (Case 2: Autoincrementing Selected, Fifo Empty Before Write)

    HRDY HCS may be brought high during strobe cycles. However, note that HRDY is gated by HCS. Host Port Interface (HPI) HPID+ Writes HPID+ Writes Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...

  • Page 29: Software Handshaking Using The Hpi Ready (Hrdy) Bit

    This leaves the host bus inactive and available to the host for HPIC reads to poll the HRDY bit. SPRUGK7A – March 2009 – Revised July 2010 Software Handshaking Using the HPI Ready (HRDY) Bit Copyright © 2009–2010, Texas Instruments Incorporated Host Port Interface (HPI)

  • Page 30: Interrupts Between The Host And The Cpu

    DSPINT bit DSPINT=0 CPU writes 1 to DSPINT bit Interrupt to CPU) pending DSPINT=1 CPU writes 0 to DSPINT bit Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Section 5.1. Section 5.2. Figure 27 SPRUGK7A – March 2009 – Revised July 2010...

  • Page 31: Cpu-To-Host Interrupt State Diagram

    Host writes 1 to HINT bit Interrupt to HINT bit active HINT bit=1 HINT signal is low Host writes 0 to HINT bit Copyright © 2009–2010, Texas Instruments Incorporated Interrupts Between the Host and the CPU Host Port Interface (HPI)

  • Page 32: Fifos And Bursting

    Figure 28. FIFOs in the HPI HPI DMA read pointer Burst writes logic Burst reads HPI DMA write pointer Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Switched internal/ central external resource memory SPRUGK7A – March 2009 – Revised July 2010...

  • Page 33: Write Bursting

    HPIAW or by another non-autoincrement access, so that the write FIFO is flushed beforehand. SPRUGK7A – March 2009 – Revised July 2010 Section 6.3). Section 4 Copyright © 2009–2010, Texas Instruments Incorporated FIFOs and Bursting for more details on the HRDY bit. Host Port Interface (HPI)

  • Page 34: Fifo Flush Conditions

    HSTRB is held high), the FIFOs are held in reset, and host transactions are held off with an inactive HRDY signal. Host Port Interface (HPI) Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...

  • Page 35: Emulation And Reset Considerations

    The read and write FIFOs and the associated FIFO logic are reset (this includes a flush of the FIFOs). • Host-to-CPU and CPU-to-host interrupts are cleared. SPRUGK7A – March 2009 – Revised July 2010 Copyright © 2009–2010, Texas Instruments Incorporated Emulation and Reset Considerations Host Port Interface (HPI)

  • Page 36: Hpi Registers

    Register Description Power and Emulation Management Register Host Port Interface Control Register Host Port Interface Address Register (Write) Host Port Interface Address Register (Read) Data Register Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Section 8.2 Section 8.3 Section 8.4 Section 8.4 Section 8.5...

  • Page 37: Power And Emulation Management Register (Pwremu_Mgmt)

    The SOFT bit selects the HPI mode. The HPI runs free regardless of the SOFT bit. SPRUGK7A – March 2009 – Revised July 2010 Figure 29 31-16 Reserved 15-2 Reserved Copyright © 2009–2010, Texas Instruments Incorporated HPI Registers and described in Table SOFT FREE R/W-0 R/W-0...

  • Page 38: Host Port Interface Control Register (Hpic)

    Figure 30. Host Access Permissions Reserved HPIARWSEL R/W-0 FETCH HRDY R/W-0 Figure 31. CPU Access Permissions Reserved HPIARWSEL FETCH HRDY Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com Table and described in Table Reserved DUALHPIA HWOBSTAT R/W-0 HINT DSPINT HWOB R/W1C-0...
  • Page 39 HPID/HPIC/HPIAR/HPIAW). The second halfword is most significant (taken from the high half of HPID/HPIC/HPIAR/HPIAW). SPRUGK7A – March 2009 – Revised July 2010 Section 7.2, an active host cycle is allowed to complete before the reset process Copyright © 2009–2010, Texas Instruments Incorporated HPI Registers Host Port Interface (HPI)

  • Page 40: Host Port Interface Address Registers (Hpiaw And Hpiar)

    Description 31-0 ADDRESS Read/write address. The host must initiate this field with a word address. Host Port Interface (HPI) CAUTION 31-0 ADDRESS R/W-0 31-0 ADDRESS Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...

  • Page 41: Data Register (Hpid)

    LEGEND: R = Read only; W = Write; -n = Value after hardware reset Table 10. Data Register (HPID) Field Descriptions Field Value Description 31-0 DATA HPI data SPRUGK7A – March 2009 – Revised July 2010 Section 31-0 DATA R/W-0 Copyright © 2009–2010, Texas Instruments Incorporated HPI Registers Host Port Interface (HPI)

  • Page 42: Appendix A Revision History

    This revision history highlights the technical changes made to the document in this revision. Additions/Modifications/Deletions Table 6 Modified table Revision History Table 11. TMS320C6457 HPI Revision History Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUGK7A – March 2009 – Revised July 2010...

  • Page 43: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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