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6. The transfer is started by sound buffer empty.
7. At the end of the transfer, a Transfer Completion interrupt flag is generated.
8. Once interrupt flag is generated, the "number of transfers" is read which must be equal to 0.
9. The Transfer Complete Interrupt flag is then cleared.
10. Correctness of the transfer is verified by sound of the playing melody.
Example 3: Peripheral to Memory DMA transfer.
•
DMAC Channel 0 is configured to transfer data from a UART data register to memory.
•
UART is configured with baud rate 115200. DMA transfers are enabled for Receive buffer full event.
•
The start of transfer is triggered by typing 8 characters in the PC window running a terminal program.
In this example:
1.
The DMAC interrupts in NVIC are not enabled.
2.
DMAC Channel transfer is enabled.
3.
DMAC Channel filtering is disabled for the selected DMAC Channel.
4.
Source address incrementing is disabled.
5.
Destination address incrementing is enabled.
6.
The transfer is started by an UART receive buffer becoming full.
7.
At the end of the transfer, a DMAC Transfer Completion interrupt flag is generated.
8.
Once interrupt flag is generated, the "transfer mode" is read which must be equal to 0(STOP mode).
9.
The Transfer Complete Interrupt flag is then cleared.
10. The Memory to Peripheral transfer (ex2) is used to output characters back to the terminal window.
11. Correctness of the transfer is verified by seeing correct characters displayed in the terminal window.
Example 4: Concurrent Peripheral to Memory and Memory to Peripheral DMA transfers.
•
T16B_0 sub-channel 0 is configured for compare mode.
•
T16B_0 sub-channel 1 is configured for capture mode.
•
DMAC Channel 0 is configured to transfer data from memory to the T16B sub-channel 0 data register.
•
DMAC Channel 1 is configured to transfer data from the T16B sub-channel 1 data register to memory.
In this example:
1.
The DMAC interrupts in NVIC are enabled.
2.
DMAC Channel transfers are enabled for two channels.
3.
DMAC Channel filtering is disabled for the selected DMAC channels.
4.
The DMA transfer is started by a compare interrupt on the T16B sub-channel 0.
5.
At the end of the transfer, a DMAC Transfer Completion interrupt flag is generated on the DMAC
channel 0.
6.
Once the DMAC interrupt is generated it sets a software completion flag by software in the DMAC
interrupt service routine.
7.
The Transfer Complete Interrupt flag is then cleared.
8.
The Peripheral to Memory transfer is started by a capture interrupt on T16B sub-channel 1.
9.
At the end of the transfer, a DMAC Transfer Completion interrupt flag is generated on the DMAC
channel 1.
10. Once interrupt flag is generated it sets a software completion flag in the DMAC interrupt service routine.
11. The Transfer Complete Interrupt flag is then cleared.
12. Software detects both transfer completion.
S1C31D01 Peripheral Circuit
Sample Software Manual (Rev.3.00)
Seiko Epson Corporation
31
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