And Logic; Fig. 8-7: Example For The And Logic: Level-Change Interrupt - Addi-Data APCI-2032 Technical Description

APCI-1032, APCI-1564 and APCI-2032

AND logic

Modus_1
Modus_2
The AND logic reacts to changes in level of the selected inputs.
An interrupt is generated each time the following condition are fulfilled:
the interruptible inputs fulfill the conditions set in Modus_1, Modus_2.
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The IRQ condition is to be fulfilled during min. 50 µs. Bounces can thus be avoided.
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After an interrupt, a change in level must occur on the interruptible inputs to release
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the IRQ logic.
In the figure below both channels 0/4 and 1/5 react to high level.
(Modus_1 = 11).

Fig. 8-7: Example for the AND logic: Level-change interrupt

50 µs (T) after the IRQ condition has been fulfilled, an interrupt is generated.
48
Disable High Low
0 1 0
0 0 1
High/Low
1
1
Functions of the board