Interrupt Control; Or Logic; Fig. 8-5: Interrupt Control (Or Logic) - Addi-Data APCI-2032 Technical Description

APCI-1032, APCI-1564 and APCI-2032
Modus_1 reacts to rising edge or high level.
Modus_2 reacts to falling edge or low level.
The registers are set as follows:
Channels 0 to 15: interruptible inputs on the APCI-1032
First channel: 0
Channels 4 to 19: interruptible inputs on the APCI-1564
First channel: 4

Interrupt control

The interrupt logic is blocked after an interrupt has occurred. It is released at the end of
the interrupt routine. In the interrupt routine the board does not react to modification of
the inputs. Another interrupt is generated when an interruptible edge or status
modification occurs.
An interrupt routine is handled after T
(approx. 100 µs; Test PC: Athlon 550 MHz, Windows NT4.0).
The time T depends on the counting capacity, the load of the system and other factors.
0

OR logic

Modus_1
Modus_2
The OR logic reacts to rising or falling edges.
An interrupt is generated when on an interruptible input an edge modification which
fulfills the interrupt conditions set in Modus_1 and Modus_2 occurs.
46

Fig. 8-5: Interrupt control (OR logic)

0
Disable Rising Falling
0 1 0
0 0 1
.
Rising/falling
1
1
Functions of the board