Additional Features; About The Core; Recommended Design Experience - Xilinx LogiCORE IP Product Manual

Additional Features

20-Gigabit XAUI (Double XAUI) Support
By running the XAUI interface at twice the normal clock and line rates, 20-Gigabit data rate
can be achieved. For devices and speed grades, see
for the core for the specific devices supported.

About the Core

The XAUI core is a Xilinx
the Xilinx IP Center. For detailed information about the core, see the

Recommended Design Experience

Although the XAUI core is a fully-verified solution, the challenge associated with
implementing a complete design varies depending on the configuration and functionality
of the application. For best results, previous experience building high performance,
pipelined Field Programmable Gate Array (FPGA) designs using Xilinx implementation
software and Xilinx Design Constraints (XDC) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
XAUI v12.3 Product Guide
PG053 April 6, 2016
®
Intellectual Property (IP) core, included in the latest IP Update on
www.xilinx.com
Chapter 1:
Speed Grades. Consult the release notes
XAUI product
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Overview
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