Chapter 1: Overview - Xilinx LogiCORE IP Product Manual

Overview
XAUI is a four-lane, 3.125 Gb/s-per-lane serial interface. Each lane is a differential pair
carrying current mode logic (CML) signaling, and the data on each lane is 8B/10B encoded
before transmission. Special code groups are used to allow each lane to synchronize at a
word boundary and to deskew all four lanes into alignment at the receiving end. The XAUI
standard is fully specified in clauses 47 and 48 of the 10-Gigabit Ethernet IEEE 802.3-2012
specification.
The XAUI standard was initially developed as a means to extend the physical separation
possible between Media Access Controller (MAC) and PHY components in a 10-Gigabit
Ethernet system distributed across a circuit board and to reduce the number of interface
signals in comparison with the XGMII (10-Gigabit Ethernet Media Independent Interface).
Figure 1-1 shows a block diagram of the XAUI core implementation. The major functional
blocks of the core include the following:
• Transmit Idle Generation Logic creates the code groups to allow synchronization and
alignment at the receiver.
• Synchronization State Machine (one per lane) identifies byte boundaries in incoming
serial data.
• Deskew State Machine de-skews the four received lanes into alignment.
• Optional MDIO Interface is a two-wire low-speed serial interface used to manage the
core.
• Four Device-Specific Transceivers (integrated in the FPGAs) provide the high-speed
transceivers as well as 8B/10B encode and decode and elastic buffering in the receive
datapath.
XAUI v12.3 Product Guide
PG053 April 6, 2016
www.xilinx.com
Chapter 1
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