Table of Contents
Advertisement
X-Ref Target - Figure 1-1
FPGA
User Logic
64+8
64+8
mdc
mdio
Figure 1‐1: Architecture of the XAUI IP Core with Client-Side User Logic
XAUI v12.3 Product Guide
PG053 April 6, 2016
Core
Core
Encrypted HDL
Synchronization
Idle
Generation
Synchronization
Synchronization
Synchronization
Management
clk156_out
www.xilinx.com
Chapter 1:
Transceiver
Transceiver
Transceiver
Transceiver
Clocks and
Reset
Logic
Send Feedback
Overview
Lane 0
Lane 1
Lane 2
Lane 3
Reference
clock
Reset
X13667
7
Advertisement
Table of Contents
Need help?
Do you have a question about the LogiCORE IP and is the answer not in the manual?
Questions and answers