Xilinx LogiCORE IP Product Manual page 113

Detailed Example Design
Figure 8-1 and
different configurations of the shared logic feature for 7 series FPGAs.
X-Ref Target - Figure 8-1
Virtex7/Kintex7/Artix7 FPGA
component_name_example_design.vhd/v
Reg
In
component_name_support_clocking.vhd/v
Support
Clocking
Reg
Out
Figure 8‐1: Example HDL Wrapper for XAUI with Shared Logic in the Example Design
XAUI v12.3 Product Guide
PG053 April 6, 2016
Figure 8-2 illustrate the top-level example design for the core with the two
component_name.vhd/v
XAUI Encrypted HDL
component_name_clk_clocking.vhd/v
component_name_clk_resets.vhd/v
(7-Series FPGAs)
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component_name_gt_wrapper.vhd/v
component_name_gt_wrapper_gt.vhd/v
component_name_gt_wrapper_gt.vhd/v
Clock Logic
component_name_gt_wrapper_gt.vhd/v
component_name_gt_wrapper_gt.vhd/v
Reset Logic
Chapter 8
Transceiver
Transceiver
Transceiver
COMMON
Transceiver
Transceiver
X13673
113
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