Xilinx LogiCORE IP Product Manual page 101

7 Series FPGA GTP Transceivers
A single IBUFDS_GTE2 module is used to feed the reference clock to the GTPE2_COMMON
PLL. The IBUFDS_GTE2 is included in the Shared Logic level of hierarchy and so can be
included either in the example design or alternatively inside the core. See
Figure 6-12 respectively for the shared logic to be included in the example design or in the
core.
X-Ref Target - Figure 6-11
refclk_p
refclk_n
IBUFDS_GTE2
Shareable logic
clk156_out
Figure 6‐11: Clock Scheme for Internal Client-Side Interface 7 Series FPGA GTP Transceiver
XAUI v12.3 Product Guide
PG053 April 6, 2016
refclk
XAUI Encrypted HDL
usrclk
BUFG
Clock Logic
BUFG
dclk
Shared Logic in Example Design
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Chapter 6:
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CORE
clk156
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Design Considerations
Figure 6-11 and
GTPE2_COMMON
GTREFCLK0
PLL0OUTCLK
PLL1OUTCLK
PLL0OUTREFCLK
PLL1OUTREFCLK
GTPE2_CHANNEL
PLL0REFCLK
PLL1REFCLK
PLL0CLK
PLL1CLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXOUTCLK
DCLK
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