Xilinx LogiCORE IP Product Manual page 65

MDIO Registers 4.5 and 4.6: PHY XS Devices in Package
Figure 2-33 shows the MDIO Registers 4.5 and 4.6: PHY XS Devices in Package.
X-Ref Target - Figure 2-33
Table 2-49 shows the PHY XS Devices in Package registers bit definitions.
Table 2‐49: PHY XS Devices in Package Registers Bit Definitions
Bit Name
Vendor-specific
4.6.15
Device 2 present
Vendor-specific
4.6.14
Device 1 present
4.6.13:0 Reserved
4.5.15:6 Reserved
4.5.5 DTE XS Present
4.5.4 PHY XS Present
4.5.3 PCS Present
4.5.2 WIS Present
4.5.1 PMA/PMD Present
Clause 22 device
4.5.0
present
XAUI v12.3 Product Guide
PG053 April 6, 2016
15 14 13
Reg 4.6
15
Reg 4.5
Figure 2‐33: PHY XS Devices in Package Registers
Description
The block always returns 0 for this bit.
The block always returns 0 for this bit.
The block always returns 0 for these bits.
The block always returns 0 for these bits.
The block always returns 0 for this bit.
The block always returns 1 for this bit.
The block always returns 0 for this bit.
The block always returns 0 for this bit.
The block always returns 0 for this bit.
The block always returns 0 for this bit.
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Chapter 2: Product Specification
0
6 5 4 3 2 1 0
X13705
Attributes
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
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Default Value
0
0
All 0s
All 0s
0
1
0
0
0
0
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