Functional Description - Xilinx LogiCORE IP Product Manual

Functional Description

Figure 4-3 shows a block diagram of the implementation of the XAUI core. The architecture
is similar for all supported devices. The major functional blocks of the core include the
following:
• Transmit idle generation logic
Creates the code groups to allow synchronization and alignment at the receiver.
• Synchronization state machine (one per lane)
Identifies byte boundaries in incoming serial data.
• Deskew state machine
Deskews the four received lanes into alignment.
• Optional MDIO interface
A 2-wire low-speed serial interface used to manage the core.
• Embedded FPGA transceivers. Provides high-speed transceivers as well as 8B/10B
encode and decode, and elastic buffering in the receive datapath.
XAUI v12.3 Product Guide
PG053 April 6, 2016
www.xilinx.com
Chapter 4: Core Architecture
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