Epson S5U1C17001C Manual page 279

Cmos 16-bit single chip microcontroller (c compiler package for s1c17 family) (ver. 3.2)
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Instruction List (7)
Mnemonic
Classification
Opcode
Logic operation
or
%rd, %rs
or/c
%rd, %rs
or/nc
%rd, %rs
or
%rd, sign7
soor
%rd, imm16
xoor
%rd, imm16
xor
%rd, %rs
xor/c
%rd, %rs
xor/nc
%rd, %rs
xor
%rd, sign7
sxor
%rd, imm16
xxor
%rd, imm16
not
%rd, %rs
not/c
%rd, %rs
not/nc
%rd, %rs
not
%rd, sign7
snot
%rd, imm16
xnot
%rd, imm16
Branch
jpr / jpr.d
%rb
sign10
sjpr / sjpr.d
label±imm20
sign20
xjpr / xjpr.d
label±imm24
sign24
jpa / jpa.d
%rb
imm7
sjpa / sjpa.d
label±imm20
imm20
xjpa / xjpa.d
label±imm24
imm24
jrgt / jrgt.d
sign7
sjrgt / sjrgt.d
label±imm20
sign20
xjrgt / xjrgt.d
label±imm24
sign24
Remarks
Operand
d(15:0)←rd(15:0) | rs(15:0), rd(23:16)←0
rd(15:0)←rd(15:0) | rs(15:0), rd(23:16)←0 if C = 1 (nop if C = 0)
rd(15:0)←rd(15:0) | rs(15:0), rd(23:16)←0 if C = 0 (nop if C = 1)
rd(15:0)←rd(15:0) | sign7 (with sign extension), rd(23:16)←0
rd(15:0)←rd(15:0) | imm16, rd(23:16)←0
rd(15:0)←rd(15:0) | imm16, rd(23:16)←0
rd(15:0)←rd(15:0)^rs(15:0), rd(23:16)←0
rd(15:0)←rd(15:0)^rs(15:0), rd(23:16)←0 if C = 1 (nop if C = 0)
rd(15:0)←rd(15:0)^rs(15:0), rd(23:16)←0 if C = 0 (nop if C = 1)
rd(15:0)←rd(15:0)^sign7 (with sign extension), rd(23:16)←0
rd(15:0)←rd(15:0)^imm16, rd(23:16)←0
rd(15:0)←rd(15:0)^imm16, rd(23:16)←0
rd(15:0)←!rs(15:0), rd(23:16)←0
rd(15:0)←!rs(15:0), rd(23:16)←0 if C = 1 (nop if C = 0)
rd(15:0)←!rs(15:0), rd(23:16)←0 if C = 0 (nop if C = 1)
rd(15:0)←!sign7 (with sign extension), rd(23:16)←0
rd(15:0)←!imm16, rd(23:16)←0
rd(15:0)←!imm16, rd(23:16)←0
pc←pc+2+rb
pc←pc+2+sign11; sign11={sign10,0}
pc←label±imm20
pc←pc+2+sign20
pc←label±imm24
pc←pc+2+sign24
pc←rb
pc←imm7
pc←label±imm20
pc←imm20
pc←label±imm24
pc←imm24
pc←pc+2+sign8 if !Z&!(N^V) is true; sign8={sign7,0}
pc←label±imm20 if !Z&!(N^V) is true
pc←pc+2+sign20 if !Z&!(N^V) is true
pc←label±imm24 if !Z&!(N^V) is true
pc←pc+2+sign24 if !Z&!(N^V) is true
Function
Assembly Programming
Flags
D
IL IE
C
V
Z
N
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0
↔ ↔
0

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