Wlcsp143 0.4 Mm Pitch Design Example; Table 10. Wafer Level Chip Scale Package Information; Figure 25. Via Fan-Out; Figure 26. Fmc Signal Fan-Out Routing Example - ST STM32F4 Series Application Note

Recommended PCB routing guidelines for STM32F4xxxx devices AN4488

Figure 25. Via fan-out

Figure 26. FMC signal fan-out routing example

8.5.2

WLCSP143 0.4 mm pitch design example

Table 10. Wafer level chip scale package information

Package information (mm) Design parameters (mm)
Microvia size : hole size ∅= 0.1, via land: 0.2
Bump pitch : 0.4
Bump size : 0.25 Trace width/space : 0.07/0.05 or 0.07/0.07
Bump pad size ∅= 0.26 max – 0.22 recommended
Number of rows/columns : 13x11
Non-solder mask defined via underbump Solder mask opening bump ∅=0.3 min (for 0.26
allowed diameter pad)
42/50 AN4488 Rev 7