Flexible Memory Controller (Fmc) Interface; Quadrature Serial Parallel Interface (Quad Spi) - ST STM32F4 Series Application Note

AN4488
8.4.2

Flexible memory controller (FMC) interface

Interface connectivity
The FMC controller and in particular SDRAM memory controller which has many signals,
most of them have a similar functionality and work together. The controller I/O signals could
be split in four groups as follow:
• An address group which consists of row/column address and bank address.
•
A command group which includes the row address strobe (NRAS), the column address
strobe (NCAS), and the write enable (SDWE).
•
A control group which includes a chip select bank1 and bank2 (SDNE0/1), a clock
enable bank1 and bank2 (SDCKE0/1), and an output byte mask for the write access
(DQM).
• A data group/lane which contains 8 signals (a): the eight D (D7–D0) and the data mask
(DQM).
Note: It depends of the used memory: SDRAM with x8 bus widths have only one data group, while
x16 and x32 bus-width SDRAM have two and four lanes, respectively.
Interface signal layout guidelines:
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50Ω ± 10%
•
The maximum trace length should be below 120mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used.
•
Reduce the crosstalk, place data tracks on the different layers from the address and
control lanes, if possible. Ho wever, when the data and address/control tracks coexist
on the same layer they must be isolated from each other by at least 5 mm.
• Match the trace lengths for the data group within ± 10 mm of each other to diminish the
skew. Serpentine traces (back and forth traces in an "S" pattern to increase trace
length) can be used to match the lengths.
•
Placing the clock (SDCLK) signal on an internal layer, minimizes the noise (EMI).
•
Route the clock signal at least 3x of the trace away from others signals. Use as less
vias as possible to avoid impedance change and reflection. Avoid using serpentine
routing.
•
Match the clock traces to the data /address group traces within ±10mm.
•
Match the clock traces to each signal trace in the address and command groups to
within ±10mm (with maximum of <= 20mm).
•
Trace the capacitances:
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8.4.3

Quadrature serial parallel interface (Quad SPI)

Interface connectivity
The QUADSPI is a specialized communication interface targeting single, dual or Quad SPI
Recommended PCB routing guidelines for STM32F4xxxx devices
At 3.3 V keep the trace within 20 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 30pF.
At 1.8 V keep the trace within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20pF.
AN4488 Rev 7 39/50
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