Atmel 8051 Hardware Manual
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Atmel 8051 Hardware Manual

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  • Page 1 Atmel 8051 Microcontrollers Hardware Manual...

  • Page 2: Table Of Contents

    Table of Contents Section 1 The 8051 Instruction Set............... 1-2 Program Status Word................1-2 Addressing Modes ..................1-3 Arithmetic Instructions................1-5 Logical Instructions ...................1-6 Data Transfers ..................1-7 External RAM ..................1-10 Lookup Tables ..................1-10 Boolean Instructions ................1-11 Jump Instructions ..................1-13 1.10 Read-Modify-Write Instruction Features ..........1-15 1.11 Instruction Set Summary.................1-16...

  • Page 3: The 8051 Instruction Set

    Section 1 The 8051 Instruction Set The 8051 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for one-bit vari- ables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing.

  • Page 4: Addressing Modes

    (0.0)-Bank 0(00H-07H) (0.1)-Bank 1(08H-0FH) (1.0)-Bank 2(10H-17H) (1.1)-Bank 3(18H-1FH) Addressing The addressing modes in the 8051 instruction set are as follows: Modes 1.2.1 Direct Addressing In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 Lowest bytes of internal Data RAM and SFRs can be directly addressed.
  • Page 5 Another type of indexed addressing is used in the “case jump” instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data. Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 6: Arithmetic Instructions

    For example, the ADD A, <byte> instruction can be written as: ADD A,7FH (direct addressing) ADD A,@ R0(indirect addressing) ADD A,R7 (register addressing) ADD A,# 127(immediate constant) Table 1-2. A list of the Atmel 8051 Arithmetic Instructions. Execution Time in X1 Mode Mnemonic Operation Addressing Modes @12 MHz (µs) ADD A, <byt>e...

  • Page 7: Logical Instructions

    ANL A, # 53H(immediate constant) All of the logical instructions that are Accumulator specific execute in 1 µs (using a 12 MHz clock and X1 mode). The others take 2 µs. Table 1-3. A list of the Atmel 8051 Logical Instructions Execution Time Mnemonic...

  • Page 8: Data Transfers

    128 bytes of data RAM can be accessed only by indirect, and SFR space only by direct addressing. Note that in all 8051 devices, the stack resides in on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into the stack.
  • Page 9 ACC and @ Ri exchange low XCHD A, @Ri nibbles The Upper 128 are not implemented in the 8 standard 8051, nor in their ROMless. With these devices, if the SP points to the Upper 128 PUSHed bytes are lost, and POPped bytes are indeterminate.
  • Page 10 First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed which leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 11: External Ram

    The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table base, and the table is accessed through a subroutine. First the num- ber of the desired entry is loaded into the Accumulator, and the subroutine is called: Atmel 8051 Microcontrollers Hardware Manual 1-10 4316B–8051–02/04...

  • Page 12: Boolean Instructions

    MOVC A, @A + PC Read Pgm Memory at (A + PC) Boolean 8051 devices contain a complete Boolean (single-bit) processor. The internal RAM con- Instructions tains 128 addressable bits, and the SFR space can support up to 128 other addressable bits.
  • Page 13 This is a signed (two’s complement) offset byte which is added to the PC in two’s complement arithmetic if the jump is executed. The range of the jump is therefore -128 to +127 Program Memory bytes relative to the first byte following the instruction. Atmel 8051 Microcontrollers Hardware Manual 1-12 Rev. 4316B–8051–02/04...

  • Page 14: Jump Instructions

    Direct Addressed bit in Internal Data RAM or Special Function Register. Jump Table 1-11 shows the list of unconditional jumps. Instructions Table 1-11. Unconditional Jumps in Atmel 8051 Mnemonic Operation Execution Time @ 12MHz (µs) JMP addr...
  • Page 15 If there is no interrupt in progress at the time RETI is executed, then the RETI is functionally identical to RET. Table 1-12 shows the list of conditional jumps available to the Atmel 8051 user. All of these jumps specify the destination address by the relative offset method, and so are limited to a jump distance of -128 to + 127 bytes from the instruction following the condi- tional jump instruction.

  • Page 16: Read-Modify-Write Instruction Features

    The 8051 Instruction Set Table 1-12. Conditional Jumps in Atmel 8051 Devices Execution Time Mnemonic Operation Addressing Modes @ 12MHz (µs) JZ rel Jump if A = 0 Accumulator only Jump if A ≠ 0 JNZ rel Accumulator only Decrement and jump if DJNZ <byte>,rel...

  • Page 17: Instruction Set Summary

    Decimal Adjust Accumulator Note: 1. All mnemonics copyrighted © Intel Corp., 1980. Mnemonic Description Byte Oscillator Period LOGICAL OPERATIONS AND Register to Accumulator A,direct AND direct byte to Accumulator A,@R AND indirect RAM to Accumulator Atmel 8051 Microcontrollers Hardware Manual 1-16 4316B–8051–02/04...
  • Page 18 Move direct byte to register ,#data Move immediate data to register direct,A Move Accumulator to direct byte direct,R Move register to direct byte direct,direct Move direct byte to direct direct,@R Move indirect RAM to direct byte 1-17 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 19 OR direct bit to Carry C,/bit OR complement of direct bit to Carry C,bit Move direct bit to Carry bit,C Move Carry to direct bit Jump if Carry is set Jump if Carry not set Atmel 8051 Microcontrollers Hardware Manual 1-18 4316B–8051–02/04...
  • Page 20 Jump if Not Equal CJNE ,#data,rel Compare immediate to indirect and Jump if Not Equal DJNZ ,rel Decrement register and Jump if Not Zero DJNZ direct,rel Decrement direct byte and Jump if Not Zero No Operation 1-19 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 21: Instructions That Affect Flag Settings

    ORL C,bit ORL C,/bit MOV C,bit CJNE SETB C Note: Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings. Atmel 8051 Microcontrollers Hardware Manual 1-20 4316B–8051–02/04...

  • Page 22: Instruction Table

    The 8051 Instruction Set 1.13 Instruction Table Table 1-14 shows the Hex value of each instruction detailing the: byte size number of cycles flags modified by the instruction Table 1-14. 8051 Instruction Table 1-21 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 23 The 8051 Instruction Set Table 1-14. 8051 Instruction Table (Continued) Atmel 8051 Microcontrollers Hardware Manual 1-22 4316B–8051–02/04...
  • Page 24 The 8051 Instruction Set Table 1-14. 8051 Instruction Table (Continued) 1-23 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 25: Instruction Definitions

    Cycles: 2 Encoding: a10 Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ← (PC (SP) ← (SP) + 1 ((SP)) ← (PC 15-8 ) ← page address 10-0 Atmel 8051 Microcontrollers Hardware Manual 1-24 4316B–8051–02/04...
  • Page 26 (A) ← (A) + (direct) ADD A,@R Bytes: 1 Cycles: 1 Encoding: Operation: ADD (A) ← (A) + ((R ADD A,#data Bytes: 2 Cycles: 1 Encoding: immediate data Operation: ADD (A) ← (A) + #data 1-25 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 27 ADDC A,@R Bytes: 1 Cycles: 1 Encoding: Operation: ADDC (A) ← (A) + (C) + ((R ADDC A,#data Bytes: 2 Cycles: 1 Encoding: immediate data Operation: ADDC (A) ← (A) + (C) + #data Atmel 8051 Microcontrollers Hardware Manual 1-26 4316B–8051–02/04...
  • Page 28 Example: The label JMPADR is at program memory location 0123H. The following instruction, AJMP JMPADR is at location 0345H and loads the PC with 0123H. Bytes: 2 Cycles: 2 Encoding: a10 Operation: AJMP (PC) ← (PC) + 2 ) ← page address 10-0 1-27 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 29 Operation: ANL ∧ (A) ← (A) A,direct Bytes: 2 Cycles: 1 Encoding: direct address Operation: ANL ∧ (A) ← (A) (direct) A,@R Bytes: 1 Cycles: 1 Encoding: Operation: ANL ∧ (A) ← (A) Atmel 8051 Microcontrollers Hardware Manual 1-28 4316B–8051–02/04...
  • Page 30 ;LOAD CARRY WITH INPUT PIN STATE C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7 C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG C,bit Bytes: 2 Cycles: 2 Encoding: bit address Operation: ANL ∧ (C) ← (C) (bit) 1-29 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 31 Operation: (PC) ← (PC) + 3 IF (A) < > (direct) THEN (PC) ← (PC) + relative offset IF (A) < (direct) THEN (C) ← 1 ELSE (C) ← 0 Atmel 8051 Microcontrollers Hardware Manual 1-30 4316B–8051–02/04...
  • Page 32 Operation: (PC) ← (PC) + 3 IF ((R )) < > data THEN (PC) ← (PC) + relative offset IF ((R )) < data THEN (C) ← 1 ELSE (C) ← 0 1-31 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 33 Example: Port 1 has previously been written with 5DH (01011101B). The following instruction,CLR P1.2 leaves the port set to 59H (01011001B). Bytes: 1 Cycles: 1 Encoding: Operation: CLR (C) ← 0 Bytes: 2 Cycles: 1 Encoding: bit address Operation: CLR (bit) ← 0 Atmel 8051 Microcontrollers Hardware Manual 1-32 4316B–8051–02/04...
  • Page 34 Example: Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,CPL P1.1CPL P1.2 leaves the port set to 5BH (01011011B). Bytes: 1 Cycles: 1 Encoding: Operation: CPL (C) ← Bytes: 2 Cycles: 1 Encoding: bit address Operation: CPL (bit) ← (bit) 1-33 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 35 -contents of Accumulator are BCD ∨ [[(A ) > 9] [(AC) = 1]] ) ← (A THEN (A ) + 6 ∨ [[(A ) > 9] [(C) = 1]] ) ← (A THEN (A ) + 6 Atmel 8051 Microcontrollers Hardware Manual 1-34 4316B–8051–02/04...
  • Page 36 ) ← (R ) - 1 direct Bytes: 2 Cycles: 1 Encoding: direct address Operation: DEC (direct) ← (direct) - 1 Bytes: 1 Cycles: 1 Encoding: Operation: DEC )) ← ((R )) - 1 1-35 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 37 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV are both cleared. Bytes: 1 Cycles: 4 Encoding: Operation: DIV ← (A)/(B) 15-8 Atmel 8051 Microcontrollers Hardware Manual 1-36 4316B–8051–02/04...
  • Page 38 Cycles: 2 Encoding: direct address rel. address Operation: DJNZ (PC) ← (PC) + 2 (direct) ← (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) ← (PC) + rel 1-37 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 39 ) ← (R ) + 1 direct Bytes: 2 Cycles: 1 Encoding: direct address Operation: INC (direct) ← (direct) + 1 Bytes: 1 Cycles: 1 Encoding: Operation: INC )) ← ((R )) + 1 Atmel 8051 Microcontrollers Hardware Manual 1-38 4316B–8051–02/04...
  • Page 40 LABEL2. Bytes: 3 Cycles: 2 Encoding: bit address rel. address Operation: JB (PC) ← (PC) + 3 (bit) = 1 THEN (PC) ← (PC) + rel 1-39 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 41 LABEL2. Bytes: 2 Cycles: 2 Encoding: rel. address Operation: JC (PC) ← (PC) + 2 (C) = 1 THEN (PC) ← (PC) + rel Atmel 8051 Microcontrollers Hardware Manual 1-40 4316B–8051–02/04...
  • Page 42 LABEL2. Bytes: 3 Cycles: 2 Encoding: bit address rel. address Operation: JNB (PC) ← (PC) + 3 (bit) = 0 THEN (PC) ← (PC) + rel 1-41 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 43 Accumulator to 01H and continues at label LABEL2. Bytes: 2 Cycles: 2 Encoding: rel. address Operation: JNZ (PC) ← (PC) + 2 (A) ≠ 0 THEN (PC) ← (PC) + rel Atmel 8051 Microcontrollers Hardware Manual 1-42 4316B–8051–02/04...
  • Page 44 Cycles: 2 Encoding: addr15-addr8 addr7-addr0 Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC (SP) ← (SP) + 1 ((SP)) ← (PC 15-8 (PC) ← addr 15-0 1-43 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 45 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2. MOV A,R Bytes: 1 Cycles: 1 Encoding: Operation: MOV (A) ← (R Atmel 8051 Microcontrollers Hardware Manual 1-44 4316B–8051–02/04...
  • Page 46 ) ← (A) MOV R ,direct Bytes: 2 Cycles: 2 Encoding: direct addr. Operation: MOV ) ← (direct) MOV R ,#data Bytes: 2 Cycles: 1 Encoding: immediate data Operation: MOV ) ← #data 1-45 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 47 Operation: MOV (direct) ← ((R MOV direct,#data Bytes: 3 Cycles: 2 Encoding: direct address immediate data Operation: MOV (direct) ← #data MOV @R Bytes: 1 Cycles: 1 Encoding: Operation: MOV )) ← (A) Atmel 8051 Microcontrollers Hardware Manual 1-46 4316B–8051–02/04...
  • Page 48 Port 1 to 39H (00111001B). MOV C,bit Bytes: 2 Cycles: 1 Encoding: bit address Operation: MOV (C) ← (bit) MOV bit,C Bytes: 2 Cycles: 2 Encoding: bit address Operation: MOV (bit) ← (C) 1-47 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 49 MOVC instruction is needed to “get around” the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead. Atmel 8051 Microcontrollers Hardware Manual 1-48...
  • Page 50 MOVX instruction using R0 or R1. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H.
  • Page 51 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared. Bytes: 1 Cycles: 4 Encoding: Operation: MUL ← (A) X (B) 15-8 Atmel 8051 Microcontrollers Hardware Manual 1-50 4316B–8051–02/04...
  • Page 52 Accumulator at run-time. The instruction, P1,#00110010B sets bits 5, 4, and 1 of output Port 1. 1-51 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 53 Bytes: 2 Cycles: 1 Encoding: direct address Operation: ORL ∨ (direct) ← (direct) direct,#data Bytes: 3 Cycles: 2 Encoding: direct addr. immediate data Operation: ORL ∨ (direct) ← (direct) #data 1.14.36 ORL C,<src-bit> Atmel 8051 Microcontrollers Hardware Manual 1-52 4316B–8051–02/04...
  • Page 54 ;OR CARRY WITH THE INVERSE OF OV. C,bit Bytes: 2 Cycles: 2 Encoding: bit address Operation: ORL ∨ (C) ← (C) (bit) C,/bit Bytes: 2 Cycles: 2 Encoding: bit address Operation: ORL ∨ (C) ← (C) (bit) 1-53 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 55 Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Bytes: 2 Cycles: 2 Encoding: direct address Operation: PUSH (SP) ← (SP) + 1 ((SP)) ← (direct) Atmel 8051 Microcontrollers Hardware Manual 1-54 4316B–8051–02/04...
  • Page 56 Stack Pointer equal to 09H and returns program execution to location 0123H. Bytes: 1 Cycles: 2 Encoding: Operation: RETI ) ← ((SP)) 15-8 (SP) ← (SP) - 1 ) ← ((SP)) (SP) ← (SP) - 1 1-55 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 57 Accumulator holding the value 8BH (10001010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: Operation: RLC + 1) ← (A ) n = 0 - 6 ) ← (C) (C) ← (A Atmel 8051 Microcontrollers Hardware Manual 1-56 4316B–8051–02/04...
  • Page 58 Accumulator holding the value 62 (01100010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: Operation: RRC ) ← (A + 1) n = 0 - 6 ) ← (C) (C) ← (A 1-57 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 59 (0123H-0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH is a one-instruction infinite loop. Bytes: 2 Cycles: 2 Encoding: rel. address Operation: SJMP (PC) ← (PC) + 2 (PC) ← (PC) + rel Atmel 8051 Microcontrollers Hardware Manual 1-58 4316B–8051–02/04...
  • Page 60 SUBB A,direct Bytes: 2 Cycles: 1 Encoding: direct address Operation: SUBB (A) ← (A) - (C) - (direct) SUBB A,@R Bytes: 1 Cycles: 1 Encoding: Operation: SUBB (A) ← (A) - (C) - ((R 1-59 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 61 Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, A,@R0 leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator. Bytes: 1 Cycles: 1 Encoding: Operation: XCH Atmel 8051 Microcontrollers Hardware Manual 1-60 4316B–8051–02/04...
  • Page 62 75H (01110101B). The following instruction, XCHD A,@R0 leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. Bytes: 1 Cycles: 1 Encoding: Operation: XCHD i3-0 1-61 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 63 Accumulator at run-time. The following instruction, P1,#00110001B complements bits 5, 4, and 0 of output Port 1. Bytes: 1 Cycles: 1 Encoding: Operation: XRL (A) ← (A) V (R Atmel 8051 Microcontrollers Hardware Manual 1-62 4316B–8051–02/04...
  • Page 64 The 8051 Instruction Set 1-63 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 65: Common Features Description

    Introduction This chapter presents a comprehensive description of the on-chip hardware features of the Atmel 8051 microcontrollers. Included in this description are: The port drivers and how they function both as ports and, for Ports 0 and 2, in bus...

  • Page 66: Special Function Registers

    Common Features Description Figure 2-1. 8051 Architecture Block Diagram Note: (*)For Timer 2 only. Figure 2-1 shows a functional block diagram of the 80C51s. Special Function A map of the on-chip memory area called SFR (Special Function Register) space is Registers shown in Figure 2-1.
  • Page 67 PCON Note: Reserved User software should not write to the reserved locations, since they may be used in derivative Atmel 8051 products to invoke new features. The functions of the SFRs are described as below. 2.2.1 Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.
  • Page 68 Control Registers Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON contain control and status bits for the interrupt system, the timer/counters, and the serial port. They are described in later sections. 2-67 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 69: Oscillator And Clock Circuit

    The internal clocking signals are at half the oscillator frequency, and define the internal phases, states, and machine cycles, which are described in the next section. 2.3.1 More about the On- This section not yet available. chip Oscillator Atmel 8051 Microcontrollers Hardware Manual 2-68 4316B–8051–02/04...

  • Page 70: Cpu Timing

    2-cycle instruction that accesses external Data Memory. During a MOVX, two fetches are skipped while the external Data Memory is being addressed and strobed. Figure 2-3C and Figure 2-3D show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. 2-69 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 71 Common Features Description Figure 2-3. 80C51 fetch/Execute Sequences. 2.4.2 X2 Mode This section not yet available. Atmel 8051 Microcontrollers Hardware Manual 2-70 4316B–8051–02/04...

  • Page 72: Port Structures And Operation

    “read pin” signal from the CPU. Some instructions that read a port activate the “read latch” signal, and others activate the “read latch” signal, and others activate the “read pin” signal. 2-71 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 73 In that conditions it can be used as a high-impedance input. Because Ports 1, 2, and 3 have fixed internal pull-ups they are sometimes called “quasi- bidirectional” ports. When configured as inputs they pull high and will source current (IIL, Atmel 8051 Microcontrollers Hardware Manual 2-72 4316B–8051–02/04...
  • Page 74 The output buffer of Ports 1, 2 and 3 can each drive 3LS TTL inputs. The pins can be Interfacing driven by open-collector and open-drain outputs, but note that 0-to-1 transition will not be fast. In the CMOS device, an input 0 turns off pull-up P3, leaving only the weak pull- 2-73 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 75 (complement bit, e.g., CPL P3.0) (increment, e.g., INC P2) (decrement, e.g., DEC P2) DJNZ (decrement and jump if not zero, e.g., DJNZ P3, LABEL) MOV PX.Y,C(move carry bit to bit Y of Port X) Atmel 8051 Microcontrollers Hardware Manual 2-74 4316B–8051–02/04...

  • Page 76: Accessing External Memory

    2. Whenever the program counter (PC) contains a number that is larger than the memory size. This requires that the ROMless versions have EA wired low to enable the lower program bytes to be fetched from external memory. 2-75 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 77: Psen

    The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 to an external latch during fetches from external Program Memory. For Atmel 8051 Microcontrollers Hardware Manual 2-76 4316B–8051–02/04...
  • Page 78 Set to map XRAM data in external XRAM memory. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XXXX XX00b 2-77 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 79: Timer/Counters

    Common Features Description Timer/Counters The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit tim- ers/counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. When operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request.
  • Page 80 Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 Timer) bits. Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade (see Figure 2-10). The selected input increments the TL0 register. 2-79 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 81 (counting F /6) and takes over use of the timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer 1 is restricted when timer 0 is in mode 3. Atmel 8051 Microcontrollers Hardware Manual 2-80 4316B–8051–02/04...

  • Page 82: Timer 1

    5 bits of the TL1 register (see Figure 2-9). The upper 3 bits of the TL1 register are ignored. Prescaler overflow increments the TH1 register. 2-81 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 83 Flags are cleared when vectoring to the timer interrupt routine. Interrupts are enabled by setting bit in IE0 register. This assumes interrupts are globally enabled by setting EA bit in the IE0 register. Atmel 8051 Microcontrollers Hardware Manual 2-82 4316B–8051–02/04...
  • Page 84 Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0. Reset Value = 0000 0000b GATE1 C/T1# GATE0 C/T0# 2-83 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 85 High Byte of Timer 0. Reset Value = 0000 0000b Table 2-5. TL0 Register - TL0 (S:8Ah) Timer 0 Low Byte Register Number Mnemonic Description Low Byte of Timer 0. Reset Value = 0000 0000b Atmel 8051 Microcontrollers Hardware Manual 2-84 4316B–8051–02/04...
  • Page 86 When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. 2-85 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 87: Timer 2

    2.12 Timer 2 Timer 2 is a 16-bit timer/counter which is present in most of the Atmel 8051 microcon- trollers.The count is maintained by two 8-bit timer registers, TH2 and TL2, that are cascade connected. Like Timers 0 and 1, it can operate either as a timer or as an event counter.
  • Page 88 At overflow, the contents of the RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency, 2-87 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 89 (8-bit) (8-bit) Toggle T2OE T2MOD TIMER 2 T2EX EXF2 INTERRUPT T2CON EXEN2 T2CON 2.12.3 Timer Registers Table 2-8. T2CON Register - T2CON (S:C8h) Timer 2 Control Register EXF2 RCLK TCLK EXEN2 C/T2# CP/RL2# Atmel 8051 Microcontrollers Hardware Manual 2-88 4316B–8051–02/04...
  • Page 90 EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable Table 2-9. T2MOD Register - T2MOD (S:C9h) Timer 2 Mode Control Register T2OE DCEN 2-89 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 91 Reset Value = 0000 0000b Not bit addressable Table 2-11. TL2 Register - TL2 (S:CCh) Timer 2 Low Byte Register Number Mnemonic Description Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Atmel 8051 Microcontrollers Hardware Manual 2-90 4316B–8051–02/04...

  • Page 92: Serial Interface

    9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the par- ity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into 2-91 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 93 Table 2-17. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupts bits (TI and RI). FE/SM0 Atmel 8051 Microcontrollers Hardware Manual 2-92 4316B–8051–02/04...
  • Page 94 The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Regis- ter PCON. If SMOD = 0 (which is its value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. 2-93 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 95 When the internal Baud Rate Generator is used, the Baud Rates are determined by the Generator (BRG) BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Atmel 8051 Microcontrollers Hardware Manual 2-94 4316B–8051–02/04...
  • Page 96 The baud rate generator can be used for mode 1 or 3 (refer to Figure 2-22 on page 97), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 2-29.) 2-95 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 97 (Table 2-8). Note then the baud rates for transmit and receive can be simultaneously dif- Rates ferent. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 2-22. Atmel 8051 Microcontrollers Hardware Manual 2-96 4316B–8051–02/04...
  • Page 98 The RCAP registers may be read, but shouldn’t be written to, because a write might overlap a reload and cause write and/or reload errors. In this case, turn the Timer off (clear TR2) before accessing the Timer 2 or RCAP registers. 2-97 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 99 RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sam- pled at the P3.0 pin at S5P2 of the same machine cycle. Atmel 8051 Microcontrollers Hardware Manual 2-98 4316B–8051–02/04...
  • Page 100 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. 2-99 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 101 Common Features Description Figure 2-24. Serial Port Mode 0 Atmel 8051 Microcontrollers Hardware Manual 2-100 4316B–8051–02/04...

  • Page 102: Framing Error Detection

    (see Figure 2-26 and Figure 2-27). Figure 2-26. UART Timings in Mode 1 Start Data byte Stop SMOD0=X SMOD0=1 Figure 2-27. UART Timings in Modes 2 and 3 Start Data byte Ninth Stop SMOD0=0 SMOD0=1 SMOD0=1 2-101 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...

  • Page 103: Automatic Address Recognition

    To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Atmel 8051 Microcontrollers Hardware Manual 2-102 4316B–8051–02/04...
  • Page 104 80C51 microcontrollers that do not support automatic address recognition. Table 2-16. SADEN Register SADEN - Slave Address Mask Register (B9h) 2-103 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 105 Common Features Description Reset Value = 0000 0000b Not bit addressable Table 2-17. SADDR Register SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable Atmel 8051 Microcontrollers Hardware Manual 2-104 4316B–8051–02/04...
  • Page 106 Set by hardware at the end of the 8th bit time in mode 0, see Figure 2-26. and Figure 2-27. in the other modes. Reset Value = 0000 0000b Bit addressable Table 2-18. SADEN Register SADEN - Slave Address Mask Register for UART (B9h) Reset Value = 0000 0000b Table 2-19. SADDR Register 2-105 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 107 Reset Value = XXXX XXXXb Table 2-21. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) Reset Value = 0000 0000b EXF2 RCLK TCLK EXEN2 C/T2# CP/RL2# Atmel 8051 Microcontrollers Hardware Manual 2-106 4316B–8051–02/04...
  • Page 108 Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable SMOD1 SMOD0 2-107 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 109 Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. TBCK RBCK Atmel 8051 Microcontrollers Hardware Manual 2-108 4316B–8051–02/04...

  • Page 110: Interrupts

    If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will 2-109 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 111 (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as shown below. Table 2-23. Source Vector Address 0003H 000BH 0013H Atmel 8051 Microcontrollers Hardware Manual 2-110 4316B–8051–02/04...
  • Page 112 4 cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 8 cycles. 2-111 Atmel 8051 Microcontrollers Hardware Manual 4316B–8051–02/04...
  • Page 113 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

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