I2C_State - State Register - Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

21.5.5 I2C_STATE - State Register

Offset
0x010
Reset
Access
Name
Bit Name
31:8 Reserved
7:5 STATE
The state of any current transmission. Cleared if the I2C module is idle.
Value
0
1
2
3
4
5
6
4 BUSHOLD
Set if the bus is currently being held by this I2C module.
3 NACKED
Set if a NACK was received and STATE is ADDRACK or DATAACK.
2 TRANSMITTER
Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a mas-
ter receiver, a slave receiver or the current mode is not known.
1 MASTER
Set when operating as an I2C master. When cleared, the system may be operating as an I2C slave.
0 BUSY
Set when the bus is busy. Whether the I2C module is in control of the bus or not has no effect on the value of this bit.
When the MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command
or a bus idle timeout to force the I2C module out of the BUSY state.
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Bit Position
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
ventions
0x0 R Transmission State
Mode Description
IDLE No transmission is being performed.
WAIT Waiting for idle. Will send a start condition as soon as the bus is
idle.
START Start transmit phase
ADDR Address transmit or receive phase
ADDRACK Address ack/nack transmit or receive phase
DATA Data transmit or receive phase
DATAACK Data ack/nack transmit or receive phase
0x0 R Bus Held
0x0 R Nack Received
0x0 R Transmitter
0x0 R Master
0x1 R Bus Busy
Reference Manual
I2C - Inter-Integrated Circuit Interface
Rev. 0.4 | 592
1.2 Con-