System Clocks - Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

Reference Manual
CMU - Clock Management Unit
Note: This figure does not necessarilly show every clock for every peripheral. These are documented in the register descriptions.

8.3.1 System Clocks

8.3.1.1 SYSCLK - Bus Clock
SYSCLK is the selected System Clock. HCLK is an optionally prescaled version of SYSCLK. PCLK is an optionally prescaled version of
HCLK. The SYSCLK, and therefore HCLK and PCLK, can be driven by a high-frequency oscillator or be driven from a pin. By default,
the FSRCO is selected as the bootup oscillator. To change the selected clock source, write to the CLKSEL bitfield in
CMU_SYSCLKCTRL. If an invalid option is programmed into CLKSEL, FSRCO will be selected. The SYSCLK is running in EM0 Active
and EM1 Sleep and is automatically stopped in EM2 DeepSleep.
The prescaler setting can be changed dynamically and the new setting takes effect immediately. When switching to a higher frequency
oscillator source, prescaler setting should be adjusted before clock selection to prevent over clocking. For the same reason, when
switching to a lower frequency oscillator source, prescaler setting cannot be adjusted until the clock selection is made.
The HFXO clock is fed directly to the Radio Transceiver. The clock received by the Radio Transceiver is therefore not affected by the
selected clock source for SYSCLK nor by any clock prescaler.
8.3.1.2 HCLK - AHB Clock
HCLK is a prescaled version of SYSCLK. This clock drives the AHB bus interface. Example modules include the CPU, Cache, Bus
Matrix, MSC, RAM, LDMA and GPIO. HCLK can be prescaled by setting HCLKPRESC in CMU_SYSCLKCTRL to DIV2 or DIV4. This
prescales HCLK to all AHB bus clocks and is typically used to save energy in applications where the system is not required to run at the
highest frequency. The setting can be changed dynamically and the new setting takes effect immediately. Some of the modules that are
driven by this clock can be clock gated completely when not in use. This is done by clearing the module enable (EN) bit in the module's
EN register.
8.3.1.3 PCLK - APB Clock
PCLK is a prescaled version of HCLK. This clock drives the APB bus interface. Example modules include USART and I2C. PCLK can
be prescaled by setting PCLKPRESC in CMU_SYSCLKCTRL to DIV2. This prescales PCLK to all APB bus clocks and is necessary to
prevent PCLK from exceeding the maximum frequency of 50MHz. The setting can be changed dynamically and the new setting takes
effect immediately. Some of the peripherals that are driven by this clock can be clock gated completely when not in use. This is done by
clearing the module enable (EN) bit in the module's EN register.
8.3.1.4 LSPCLK - Low Speed APB Clock
LSPCLK is a prescaled version of PCLK. This clock drives the Low Speed APB bus interface. Example modules include I2C. LSPCLK
is always prescaled by two. This prescales LSPCLK to all Low Speed APB bus clocks and is necessary to prevent LSPCLK from ex-
ceeding the maximum frequency of 25MHz. Some of the peripherals that are driven by this clock can be clock gated completely when
not in use. This is done by clearing the module enable (EN) bit in the module's EN register.
8.3.1.5 HCLKRADIO - AHB Radio Clock
HCLKRADIO is fed from HFXO which drives the radio subsystem including an asynchronous bus bridge. Some of the radio peripherals
that are driven by this clock can be clock gated completely when not in use. This is done by clearing the module enable (EN) bit in the
module's EN register. The radio peripherals can also be gated simultaneously by clearing the EN bit in the CMU_RADIOCLKCTRL reg-
ister. This action also shuts off the asynchronous bus bridge. When the asynchronous bus bridge is off, any access to the radio regis-
ters will result in a bus fault.
After enabling the radio asynchronous bus bridge by setting the EN bit in the CMU_RADIOCLKCTRL register, user should check the
radio clock running status bit in CMU_STATUS.RADIOCLKRUNNING before attempting transfers to the radio subsystem. Otherwise,
there will be a long peformance penalty on the first transfer, because the bus will be stalled until the radio clock turns on to receive the
transfer. If HFXO is not already running, this can be a long startup time.
Before disabling the radio asynchronous bus bridge by clearing the EN bit in the CMU_RADIOCLKCTRL register, user must ensure no
activity is ongoing across AHB to host system. Doing so can lock up the entire bus, due to handshaking in the asynchronous bridge
crossing.
silabs.com | Building a more connected world. Rev. 0.4 | 138