Timer_Ccx_Cfg - Cc Channel Configuration Register - Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register

Offset
0x060
Reset
Access
Name
Bit Name
31:22 Reserved
21 ICFWL
Sets the watermark level for generation of the ICFWLFULL interrupt and DMA requests. ICFWLFULL will be set and
DMA requests may be generated if the number of free FIFO entries is less than or equal to ICFWL.
20 FILT
Enable digital filter.
Value
0
1
19 PRSCONF
Select PRS pulse or level for PRS output.
Value
0
1
18:17 INSEL
Select Compare/Capture channel input.
Value
0
1
2
3
16:5 Reserved
4 COIST
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Bit Position
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
ventions
0x0 RW Input Capture FIFO watermark level
0x0 RW Digital Filter
Mode Description
DISABLE Digital Filter Disabled
ENABLE Digital Filter Enabled
0x0 RW PRS Configuration
Mode Description
PULSE Each CC event will generate a one EM01GRPACLK cycle high
pulse
LEVEL The PRS channel will follow CC out
0x0 RW Input Selection
Mode Description
PIN TIMERnCCx pin is selected
PRSSYNC Synchornous PRS selected
PRSASYNCLEVEL Asynchronous Level PRS selected
PRSASYNCPULSE Asynchronous Pulse PRS selected
To ensure compatibility with future devices, always write bits to 0. More information in
ventions
0x0 RW Compare Output Initial State
Reference Manual
TIMER - Timer/Counter
1.2 Con-
1.2 Con-
Rev. 0.4 | 471