Msc - Memory System Controller; Introduction - Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

6. MSC - Memory System Controller

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6.1 Introduction

The Memory System Controller (MSC) is the program memory unit of the EFR32xG21 microcontroller. The flash memory is readable
and writable from both the Cortex-M33 and DMA. The flash memory is divided into two blocks: the main block and the information
block. Program code is normally written to the main block. The information block is available for special user data. There is also a read-
only page in the information block containing system and device calibration data. Flash read and write operations are supported in the
energy modes EM0 and EM1.
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MSC - Memory System Controller
Quick Facts
What?
The user can perform Flash memory read, read con-
figuration, and write operations through the Memory
System Controller (MSC). SRAM operation may be
configured though System Configuration (SYSCFG).
Why?
The MSC allows the application code, user data,
and flash lock bits to be stored in non-volatile Flash
memory. Certain memory system functions, such as
program memory wait-states are also configured
from the MSC peripheral register interface, giving
the developer the ability to dynamically customize
the memory system performance, security level, en-
ergy consumption and error handling capabilities to
the requirements at hand.
How?
The MSC integrates a low-energy Flash IP with a
charge pump, enabling minimum energy consump-
tion while eliminating the need for external program-
ming voltage to erase the memory. An easy to use
write and erase interface is supported by an internal,
fixed-frequency oscillator and autonomous flash tim-
ing and control reduces software complexity while
not using other timer resources.
A highly efficient low energy instruction cache re-
duces the number of flash reads significantly, thus
saving energy. Performance is also improved when
wait-states are used, since many of the wait-states
are eliminated. Built-in performance counters can be
used to measure the efficiency of the instruction
cache.
Instruction prefetcher improves program execution
performance by reducing the number of wait-state
cycles needed.
Reference Manual
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