Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual page 496

20.3.2.11 Clock Recovery and Filtering
The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling
mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors.
When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate
generator is synchronized with the incoming frame.
For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity. These
samples are aimed at the middle of the bit-periods, as visualized in
With OVS=0 in USARTn_CTRL, the start and data bits are thus sampled at locations 8, 9 and 10 in the figure, locations 4, 5 and 6 for
OVS=1 and locations 3, 4, and 5 for OVS=2. The value of a sampled bit is determined by majority vote. If two or more of the three bit-
samples are high, the resulting bit value is high. If the majority is low, the resulting bit value is low.
Majority vote is used for all oversampling modes except 4x oversampling. In this mode, a single sample is taken at position 3 as shown
in Figure 20.7 USART Sampling of Start and Data Bits on page
Majority vote can be disabled by setting MVDIS in USARTn_CTRL.
If the value of the start bit is found to be high, the reception of the frame is aborted, filtering out false start bits possibly generated by
noise on the input.
Idle
0 0 0 1 2
0 1
0 1
1
If the baud rate of the transmitter and receiver differ, the location each bit is sampled will be shifted towards the previous or next bit in
the frame. This is acceptable for small errors in the baud rate, but for larger errors, it will result in transmission errors.
When the number of stop bits is 1 or more, stop bits are sampled like the start and data bits as seen in
Stop Bits when Number of Stop Bits are 1 or More on page
10 for normal mode, or 4, 5 and 6 for smart mode, the USART is ready for a new start bit. As seen in
Stop Bits when Number of Stop Bits are 1 or More on page
received correctly as long as the start-bit comes after position a for OVS=0 and OVS=3, and b for OVS=1 and OVS=2.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Start bit
3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
2 3 4 5 6
2 3 4
2 3
Figure 20.7. USART Sampling of Start and Data Bits
Figure 20.7 USART Sampling of Start and Data Bits on page
496.
2 3
7 8 1 2
5 6 1
4 1
497. When a stop bit has been detected by sampling at positions 8, 9 and
497, a stop-bit of length 1 normally ends at c, but the next frame will be
Reference Manual
Bit 0
4 5 6 7 8 9 10 11
3 4 5 6
2 3 4 5
2 3
Figure 20.8 USART Sampling of
Figure 20.8 USART Sampling of
496.
12 13
7
4
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