Read Cycle, Normal/Fast Memory (≥ 128 Kbyte), Multiple Byte Access; Write Cycle, Normal/Fast Memory (≥ 128 Kbyte), Multiple Byte Access; Read Cycle, 16 Kbytes Rom - LSI LSI53C876 Technical Manual

6.4.1.1 3.3 V PCI Timings
Table 6.24 3.3 V PCI Timing
Symbol Parameter
t Shared signal input hold time
2
t CLK to shared signal output valid
3
6-16
•
Read Cycle, Normal/Fast Memory (≥ 128 Kbyte), Multiple Byte
Access
•
Write Cycle, Normal/Fast Memory (≥ 128 Kbyte), Multiple Byte
Access
•
Read Cycle, Slow Memory (≥ 128 Kbytes)
•
Write Cycle, Slow Memory (≥ 128 Kbytes)
•

Read Cycle, 16 Kbytes ROM

•
Write Cycle, 16 Kbytes ROM
Note: When a 3.3 V source is applied to the V
LSI53C876, some of the PCI timing data in
through
is listed in
Electrical Characteristics
Table 6.35 will change. The 3.3 V PCI timing data
Table 6.24.
-I pins of the
DD
Table 6.24
Min Max
1 –
– 12
Unit
ns
ns