Dma Fifo; Parity Checking/Generation - LSI LSI53C876 Technical Manual

Figure 2.2

Parity Checking/Generation

Asynchronous
SCSI Send
PCI Interface**
X

DMA FIFO*

(32 Bits x 134)
SODL Register*
S
SCSI Interface**
X - Check parity
G - Generate 32-bit even PCI parity
S - Generate 8-bit odd SCSI parity
2.2.6 DMA FIFO
Figure 2.3 DMA FIFO Sections
134 134
.
Transfers Transfers
. .
Deep Deep
8 Bits 8 Bits
Byte Lane 3 Byte Lane 3
2-20
Asynchronous
SCSI Receive
PCI Interface**
G
DMA FIFO*
(32 Bits x 134)
SIDL Register*
X
SCSI Interface**
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is
illustrated in Figure 2.3. The default DMA FIFO size is 88 bytes to assure
compatibility with older products in the LSI53C8XX family.
The DMA FIFO size may be set to 536 bytes by setting the DMA FIFO
Size bit, bit 5, in the
8 Bits 8 Bits
Byte Lane 2 Byte Lane 2
Functional Description
Synchronous
SCSI Send
PCI Interface**
X
DMA FIFO*
(32 Bits x 134)
SODL Register*
SODR Register*
S
SCSI Interface**
Chip Test Five (CTEST5)
32 Bytes Wide 32 Bytes Wide
8 Bits 8 Bits
Byte Lane 1 Byte Lane 1
Synchronous
SCSI Receive
PCI Interface**
G
DMA FIFO*
(32 Bits x 134)
X
SCSI FIFO*
(8 or 16 Bits x 16)
X
SCSI Interface**
* = No parity protection
** = Parity protected
register.
8 Bits 8 Bits
Byte Lane 0 Byte Lane 0
. .
. . . .